Impact of LER and misaligned vias on the electric field in nanometer-scale wires

2008 IEEE International Interconnect Technology Conference, IITC

Volumn , Issue , 2008, Pages 174-176

  Stucchi, Michele ^a   Tokei, Zsolt ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; ELECTRIC FIELD EFFECTS; ELECTRIC FIELDS;

DIELECTRIC BREAKDOWN; INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE; NANO-METER SCALE;

WIRE;

EID: 50949128835     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2008.4546959     Document Type: Conference Paper

References (8)

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3. M. Stucchi, M. Bamal and K. Maex, "Impact of line-edge roughness on resistance and capacitance of scaled interconnects" Microel. Engineering, Vol. 8, Issue 11, Nov. 2007, pp.2733-2737
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7. Synopsis Raphael Reference Manual, 2006.03
8. A. Yamaguchi et al, "Characterization of Line-edge Roughness in Cu/low-k Interconnect Pattern", Solid-State Devices and Material (SSDM) International Conference, Tsukuba 2007, pp 932-933