Built-in proactive tuning system for circuit aging resilience

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2008, Pages 96-104

  Shah, Nimay ^a   Samanta, Rupak ^a   Zhang, Ming ^b   Hu, Jiang ^a   Walker, Duncan ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AGING EFFECTS; BENCHMARK CIRCUIT; CIRCUIT AGING; CIRCUIT BLOCKS; CONSTRAINED DESIGN; DYNAMIC VOLTAGE SCALING; NANOMETER VLSI; OPERATION TIME; PERFORMANCE DEGRADATION; POWER DISSIPATION; POWER EFFICIENT; POWER OVERHEAD; SPICE SIMULATIONS; TUNING SYSTEM;

DEGRADATION; FAULT TOLERANCE; PROBABILITY DENSITY FUNCTION; QUALITY ASSURANCE; SPICE; TUNING; VLSI CIRCUITS; VOLTAGE STABILIZING CIRCUITS;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 67649946059     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2008.49     Document Type: Conference Paper

References (13)

1. M. Abramovici, M. A. Breuer and A. D. Friedman, "Digital Systems Testing and Testable Design", IEEE Press, New York, 1990.
2. M. Agarwal, B. C. Paul, M. Zhang and S. Mitra, "Circuit Failure Prediction and Its Application to Transistor Aging", IEEE VLSI Test Symposium, 2007, pp. 277-286.
3. K. A. Bowman, J. W. Tschanz, N. S. Kim, J. C. Lee, C. B. Wilkerson, S.-L. L. Lu, T. Karnik and V. K. De, "Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance", IEEE ISSCC, 2008, pp. 402-403.
4. S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner and T. Mudge, "A Self-Tuning DVS Processor Using Delay-Error Detection and Correction", IEEE Journal of Solid-State Circuits, Vol.41, No.4, April 2006, pp. 792-804.
5. K. Kang, S. P. Park, K. Roy, and M. A. Alam, "Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance", Proceedings of the 2007 IEEE/ACM ICCAD, November 2007, pp 730-734.
6. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam and K. Roy, "Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits", IEEE Transactions on CAD of Integrated Circuits and Systems, Vol.26, No.4, April 2007, pp. 743-751. (Pubitemid 46479748)
7. R. Samanta, G. Venkataraman, N. Shah and J. Hu, "Elastic Timing Scheme for Energy-Efficient and Robust Performance", IEEE ISQED, 2008, pp. 537-542.
8. T. Sato and Y. Kunitake, "A Simple Flip-flop Circuit for Typical-Case Designs for DFM", IEEE ISQED, 2007, pp. 539-544.
9. J. Srinivasan, S. V. Adve, P. Bose and J. A. Rivers, "The Case for Lifetime Reliability-Aware Microprocessors", ACM/IEEE ISCA 2004, pp. 276-287.
10. J. Srinivasan, S. V. Adve, P. Bose and J. A. Rivers, "Lifetime Reliability: Towards an Architectural Solution", IEEE Micro, Vol.25, No.3, May-June 2005, pp. 70-80. (Pubitemid 41046874)
11. I. E. Sutherland, "Micropipelines", Communications of the ACM, Vol.32, No.6, June 1989, pp. 720-738.
12. J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan and V. De, "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage", IEEE Journal of Solid-State Circuits, Vol.37, No.11, November 2002, pp. 1396-1402. (Pubitemid 35432159)
13. M. Zhang, T. M. Mak, J. Tschanz, K. S. Kim, N. Seifert, and D. Lu, "Design for Resilience to Soft Errors and Variations", Proceedings of the 13th IEEE IOLTS, July 2007, pp. 23-28.