Elastic timing scheme for energy-efficient and robust performance

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 537-542

  Samanta, Rupak ^a   Venkataraman, Ganesh ^b   Shah, Nimay ^a   Hu, Jiang ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b MAGMA DESIGN AUTOMATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; CLOCK SKEWS; CONVENTIONAL APPROACH; ELECTRONIC DESIGNS; ENERGY-EFFICIENT; FEED BACK LOOPS; INTERNATIONAL SYMPOSIUM; LOW PROBABILITY; NANO-METER REGIMES; OPTIMIZATION ALGORITHMS; POWER CONSTRAINTS; POWER DISSIPATIONS; ROBUST PERFORMANCE; RUN-TIME; SAFETY MARGIN; TIMING ERRORS; TIMING VARIATIONS; VARIATION TOLERANCES;

CONSERVATION; ELECTRIC POWER UTILIZATION; ELECTRONICS ENGINEERING; ENERGY EFFICIENCY; ERROR CORRECTION; ERRORS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; NETWORKS (CIRCUITS); OPTIMIZATION; PIPELINES; REAL TIME SYSTEMS; SEQUENTIAL CIRCUITS; TIME MEASUREMENT; WIRELESS TELECOMMUNICATION SYSTEMS;

TIMING CIRCUITS;

EID: 49749096836     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479792     Document Type: Conference Paper

References (11)

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