Applying Anand model to low-temperature sintered nanoscale silver paste chip attachment

Materials and Design

Volumn 30, Issue 10, 2009, Pages 4574-4579

  Yu, Dun ji ^a   Chen, Xu ^a   Chen, Gang ^a   Lu, Guo quan ^b   Wang, Zheng qiang ^a  

^a TIANJIN UNIVERSITY   (China)

^b VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANAND MODEL; ANSYS SOFTWARE; BONDING LAYERS; CHIP ATTACHMENT; DYNAMIC MECHANICAL ANALYZER; FINAL FAILURES; FINITE ELEMENT SIMULATIONS; INELASTIC DEFORMATION; INTERFACE MATERIALS; LOW TEMPERATURES; NANOSCALE SILVER PASTE; PLASTIC STRAIN; SILVER FILM; SIMULATION RESULT; SINTERED FILMS; TENSILE BEHAVIORS;

COMPUTER SOFTWARE; NANOSTRUCTURED MATERIALS; SILVER; SIMULATORS; SINTERING; STRESS-STRAIN CURVES; STRESSES; THERMAL CYCLING;

STRAIN RATE;

EID: 67649390762     PISSN: 02641275     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.matdes.2009.04.006     Document Type: Article

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