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Volumn 53, Issue 7, 2009, Pages 792-797

Floating gate technology for high performance 8-level 3-bit NAND flash memory

Author keywords

8 Level; Disturbance; Floating gate; MLC; NAND flash

Indexed keywords

8-LEVEL; DISTURBANCE; FLOATING GATE; MLC; NAND FLASH;

EID: 67349279609     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.03.019     Document Type: Article
Times cited : (12)

References (13)
  • 1
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    • Kwak Donghwa, Park Jaekwan, Kim Keonsoo, Yim Yongsik, Ahn Soojin, Park Yoonmoon, et al. Integration technology of 30 nm generation multi-level NAND flash for 64 Gb NAND flash memory. In: Symposium on VLSI technology digest of technical papers 2-1; 2007. p. 12-3.
    • Kwak Donghwa, Park Jaekwan, Kim Keonsoo, Yim Yongsik, Ahn Soojin, Park Yoonmoon, et al. Integration technology of 30 nm generation multi-level NAND flash for 64 Gb NAND flash memory. In: Symposium on VLSI technology digest of technical papers 2-1; 2007. p. 12-3.
  • 4
    • 37649028729 scopus 로고    scopus 로고
    • A scalable stacked gate NOR/NAND flash technology compatible with high-k and metal gates for sub 45 nm generations
    • De Vos J., Haspeslagh L., Demand M., Devriendt K., Wellekens D., Beckx S., et al. A scalable stacked gate NOR/NAND flash technology compatible with high-k and metal gates for sub 45 nm generations. Integr Circ Des Technol (2006) 1-4
    • (2006) Integr Circ Des Technol , pp. 1-4
    • De Vos, J.1    Haspeslagh, L.2    Demand, M.3    Devriendt, K.4    Wellekens, D.5    Beckx, S.6
  • 5
    • 36448932248 scopus 로고    scopus 로고
    • Tanaka H, Kido M, Yahashi K, Oomura M, Katsumata R, Kito M, et al. Bit cost scalable technology with punch and plug process for ultra high density flash memory. In: Symposium on VLSI technology digests of technical papers 2-2; 2007. p. 14-5.
    • Tanaka H, Kido M, Yahashi K, Oomura M, Katsumata R, Kito M, et al. Bit cost scalable technology with punch and plug process for ultra high density flash memory. In: Symposium on VLSI technology digests of technical papers 2-2; 2007. p. 14-5.
  • 7
    • 39749099420 scopus 로고    scopus 로고
    • Shibata Noboru, Maejima Hiroshi, Isobe Katsuaki, Iwasa Kiyoaki, et al. A 70 nm 16 Gb 16-level-cell NAND flash memory. In: Symposium on VLSI circuits digest of technical papers 18-5; 2007. p. 190-1.
    • Shibata Noboru, Maejima Hiroshi, Isobe Katsuaki, Iwasa Kiyoaki, et al. A 70 nm 16 Gb 16-level-cell NAND flash memory. In: Symposium on VLSI circuits digest of technical papers 18-5; 2007. p. 190-1.
  • 9
    • 33751050873 scopus 로고    scopus 로고
    • A high cost-performance and reliable 3-level MLC NAND flash memory using virtual page cell architecture
    • Park Ki-Tae, Choi Jungdal, Cho Sungkyu, Choi Yunho, Kim Kinam. A high cost-performance and reliable 3-level MLC NAND flash memory using virtual page cell architecture. IEEE non-volatile semiconductor memory workshop; 2006. p. 34-5.
    • (2006) IEEE non-volatile semiconductor memory workshop , pp. 34-35
    • Ki-Tae, P.1    Choi, J.2    Cho, S.3    Choi, Y.4    Kinam, K.5
  • 10
    • 41149116218 scopus 로고    scopus 로고
    • Park Ki-Tae, Choi Jungdal, Sel Jongsun, Kim Viena, Kang Changseok, Shin Yoocheol, et al. A 64-cell NAND flash memory with asymmetric S/D structure for Sub-40 nm technology and beyond. In: Symposium on VLSI technology digest of technical papers; 2006. p. 19-20.
    • Park Ki-Tae, Choi Jungdal, Sel Jongsun, Kim Viena, Kang Changseok, Shin Yoocheol, et al. A 64-cell NAND flash memory with asymmetric S/D structure for Sub-40 nm technology and beyond. In: Symposium on VLSI technology digest of technical papers; 2006. p. 19-20.
  • 11
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    • A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
    • Suh K.-D., Suh B.-H., Lim Y.-H., Kim J.-K., Choi Y.-J., Koh Y.-N., et al. A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. IEEE J Solid-State Circ 31 11 (1995) 1149-1156
    • (1995) IEEE J Solid-State Circ , vol.31 , Issue.11 , pp. 1149-1156
    • Suh, K.-D.1    Suh, B.-H.2    Lim, Y.-H.3    Kim, J.-K.4    Choi, Y.-J.5    Koh, Y.-N.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.