A scalable stacked gate NOR/NAND flash technology compatible with high-k and metal gates for sub 45nm generations

2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06

Volumn , Issue , 2006, Pages

  De Vos, Joeri ^a   Haspeslagh, Luc ^a   Demand, Marc ^a   Devriendt, Katia ^a   Wellekens, Dirk ^a   Beckx, Stephan ^a   Van Houdt, Jan ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; FLASH MEMORY; GATES (TRANSISTOR); TITANIUM NITRIDE;

FLOATING GATE (FG); PLANAR STRUCTURE; STACKED GATE TECHNOLOGY;

NAND CIRCUITS;

EID: 37649028729     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2006.220783     Document Type: Conference Paper

References (7)

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4. B. Govoreanu et al., Solid-State Electronics 2005 (49) pp. 1841-1848
5. International Technology Roadmap for Semiconductors (ITRS), http://public.itrs.net
6. J.Van Houdt, IRPS 2005
7. B. Govoreanu et al., EDL Vol. 24, No 2, p. 99-101, 2003