A 64-cell NAND flash memory with asymmetric S/D structure for sub-40nm technology and beyond

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 19-20

  Park, Ki Tae ^a   Choi, Jungdal ^a   Sel, Jongsun ^a   Kim, Viena ^a   Kang, Changseok ^a   Shin, Yoocheol ^a   Roh, Ukjin ^a   Park, Jintaek ^a   Lee, Jang Sik ^a   Sim, Jaesung ^a   Jeon, Sanghun ^a   Lee, Changhyun ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH MEMORY; SEMICONDUCTOR JUNCTIONS; TECHNOLOGY TRANSFER;

FRINGE FIELDS; MULTI-LEVEL-CELL (MLC); NAND OPERATION CONDITIONS;

NAND CIRCUITS;

EID: 41149116218     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. K. Kim, IEDM, pp.333-336, 2005
2. Y-C Shin, et al., IEDM, pp.337-340, 2005