Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron

Microelectronics Journal

Volumn 40, Issue 6, 2009, Pages 979-982

  Kureshi, A K ^a   Hasan, Mohd ^a  

^a ALIGARH MUSLIM UNIVERSITY   (India)

Author keywords

Carbon nanotubes; CNFET; Deep submicron; Nanoelectronics; SRAM

Indexed keywords

32 NM TECHNOLOGIES; 6T-SRAM; BERKELEY PREDICTIVE TECHNOLOGY MODELS; CNFET; DEEP SUBMICRON; FIELD EFFECTS; HSPICE SIMULATIONS; PERFORMANCE COMPARISONS; PROCESS PARAMETER VARIATIONS; SRAM; STAND-BY LEAKAGES; STATIC-NOISE MARGINS;

CELLS; CYTOLOGY; JITTER; NANOELECTRONICS; STATIC RANDOM ACCESS STORAGE;

CARBON NANOTUBES;

EID: 67349228845     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2008.11.062     Document Type: Article

References (18)

1. R. Martel, et al., Carbon nanotube field effect transistor for logic applications, Electron Devices Meeting, 20 IEDM Technical Digest International, 2001, pp. 7.5.1-7.5.4.
2. 〈http://www-device.eecs.berkeley.edu/~bsim3/bism4.html〉
3. Deng J., Lin A., Wan G.C., and Philip Wong H.-S. Carbon nanotube transistor compact model for circuit design and performance optimization. ACM Journal on Emerging Technologies in Computing Systems 4 2 (2008) 7-19
4. Deng J., and Wong H.-S.P. A compact SPICE model for carbon-nanotube field effect transistors including non-idealities and its application-Part II: full device model and circuit performance benchmarking. IEEE Transactions on Electron Devices 54 (2007) 3195-3205
5. Raychowdhury A., Mukhopadhyay S., and Roy K. A circuit-compatible model of ballistic carbon nanotube field-effect transistors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23 (2004) 1411-1420
6. Deng J., and Wong H.-S.P. Modeling and analysis of planar gate capacitance for 1-D FET with multiple cylindrical conducting channels. IEEE Transactions on Electron Devices 54 (2007) 2377-2385
7. X. Wang, H.-S.P. Wong, P. Oldiges, R.J. Miller, Electrostatic analysis of carbon nanotube arrays, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, September 2003, pp. 163-166.
8. Frustaci F., Corsonello P., Perri S., and Cocorullo G. Techniques for leakage energy reduction in deep submicrometer cache memories. IEEE Transactions on VLSI Systems 14 11 (2006) 1238-1249
9. Knoch J., Mantl S., and Appenzeller J. Comparison of transport properties in carbon nanotube field-effect transistors with Schottky contacts and doped source/drain contacts. Elsevier's Solid State Electronics Journal 49 (2005) 73-76
10. Morifuji E., Patil D., Horowitz M., and Nishi Y. Power optimization for SRAM and its scaling. IEEE Transactions on Electron Devices 54 4 (2007) 715-722
11. Aly R., Faisal M., and Bayoumi A. Novel 7T SRAM cell for low power cache design. Proceedings of the IEEE SOC Conference (2005) 171-174
12. Gunther S.H. Managing the impact of increasing microprocessor power consumption. Intel Technology Journal Q 1 (2001) 1-9
13. Tans S., Verschueren A., and Dekker C. Room-temperature transistor based on a single carbon nanotube. Nature 393 (1998) 49-52
14. Teo K., et al. Carbon nanotube technology for solid state and vacuum electronics. IEE Proceedings-Circuits Devices and Systems 151 5 (2004) 443-451
15. Kotlyar R., Obradovic B., Matagne P., Stettler M., and Giles M.D. Assessment of room-temperature phonon-limited mobility in gated silicon nanowires. Applied Physics Letters 84 (2004) 5270-5272
16. Grossar E., Stucchi M., Maex K., and Dehaene W. Read stability and write-ability analysis of SRAM cells for nanometer technologies. IEEE Journal of Solid-State Circuits 41 (2006) 2577-2588
17. Y. Li, Chien-Sung Lu, Characteristic Comparison of SRAM Cells with 20 nm Planar MOSFET, Omega FinFET and Nanowire FinFET, Sixth IEEE Conference on Nanotechnology, vol. 1, 17-20, June 2006, pp. 339-342.
18. Bipul C., et al. Impact of a process variation on nanowire and nanotube devices performance. IEEE Transactions on Electron Devices 54 9 (2007) 2369-2375