Manufacturing challenges in double patterning lithography

IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings

Volumn , Issue , 2006, Pages 283-286

  Arnold, William ^a   Dusa, Mircea ^a   Finders, Jo ^b  

^a ASML US Inc   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; ELECTRIC CONDUCTIVITY; LITHOGRAPHY; PHOTORESISTS; PROBABILITY; SEMICONDUCTOR MATERIALS; TURBULENT FLOW;

APPLICATIONS.; CRITICAL ISSUES; CURRENT CAPABILITY; DOUBLE PATTERNING; EXPOSURE DOSE; EXPOSURE METRICS; INNOVATIVE METHODS; INTERNATIONAL SYMPOSIUM; MANUFACTURING CHALLENGES; PATTERNING PROCESSES; PREDICTIVE SIMULATIONS; SEMICONDUCTOR MANUFACTURING; SIMULATION RESULTS; SINGLE EXPOSURE; STATE OF THE ARTS;

INDUSTRIAL APPLICATIONS;

EID: 50249155836     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSM.2006.4493084     Document Type: Conference Paper

References (5)

1. M. Dusa, W. Arnold, A. Pici, "Prospects and Initial Results from Double Exposure/Double Pitch Technique" ISSM, September 2005,
2. C. M. Lim et all, "Positive and Negative Tone Double Patterning Lithography for 50nm Flash Memory," Proc. SPIE 2006, 6154-37
3. M. Maenhoudt et all, "Double Patterning Scheme for sub0.25k1 single Damascene Structures at NA==0.75, λ= 193", Proceedings SPIE Microtithography Vol. 5751-5756, March 2006, Santa Clara, CA
4. C. Pierrat et all, "Mask Fabrication Challenges," SEMI-SEMATECH LithoForum, Vancouver, May 2006
5. R. Rubingh et all, "Lithographic performance of a DualStage ArF 0.93NA Step and Scan System" Proceeedings SPIE Microlithography Vol. 5754 Conference, #5457-65, March 2006, Santa Clara, CA