PMOSFET reliability study for direct silicon bond (DSB) hybrid orientation technology (HOT)

IEEE Electron Device Letters

Volumn 28, Issue 9, 2007, Pages 815-817

  Huang, Yao Tsung ^a   Pinto, Angelo ^b   Lin, Chien Ting ^a   Hsu, Che Hua ^a   Ramin, Manfred ^b   Seacrist, Mike ^c   Ries, Mike ^c   Matthews, Kenneth ^d   Nguyen, Billy ^d   Freeman, Melissa ^d   Wilks, Bruce ^b,d   Stager, Chuck ^d   Johnson, Charlene ^d   Denning, Laurie ^d   Bennett, Joe ^d   Joshi, Sachin ^e   Chiang, Sinclair ^a   Cheng, Li Wei ^a   Lee, Tung Hsing ^a   Ma, Mike ^a   Cheng, Osbert ^a   Wise, Rick ^b   more..

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^b TEXAS INSTRUMENTS   (United States)

^c MEMC Electronic Materials Inc   (United States)

^d Advanced Technology Development Facility   (United States)

^e The University of Texas at Austin   (United States)

Author keywords

Amorphization and templated recrystallization (ATR); Direct Si bond (DSB); Hybrid orientation technology (HOT); Reliability; Solid phase epitaxy

Indexed keywords

BULK CMOS; DIRECT SI BOND (DSB); DRIVE CURRENTS; GATE OXIDES; HYBRID ORIENTATION TECHNOLOGY (HOT); NEGATIVE BIAS TEMPERATURE INSTABILITIES; ORIENTATION DEPENDENCES; P-MOSFETS; PMOSFET; SILICON BONDS; SOLID PHASE EPITAXY; SYSTEMATIC INVESTIGATIONS; TIME-DEPENDENT DIELECTRIC BREAKDOWNS;

AMORPHIZATION; CRYSTAL GROWTH; DANGLING BONDS; DIELECTRIC MATERIALS; FIELD EFFECT TRANSISTORS; GATE DIELECTRICS; HOLE MOBILITY; HYBRID MATERIALS; MOSFET DEVICES; RECRYSTALLIZATION (METALLURGY); RELIABILITY; SEMICONDUCTING SILICON COMPOUNDS; SILICON; SILICON WAFERS; TECHNOLOGY; WAFER BONDING;

CRYSTAL ORIENTATION;

EID: 65249101289     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.902613     Document Type: Article

References (12)

1. M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D'Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, and H. Ng, "High performance CMOS fabricated on hybrid substrate with different crystal orientations," in IEDM Tech. Dig. 2003, pp. 18.7.1-18.7.4.
2. M. Yang, E. Gusev, M. Ieong, O. Gluschenkov, D. Boyd, K. Chan, P. Kozlowski, C. D'Emic, R. Sicina, P. Jamison, and A. Chou, "Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics," IEEE Electron Device Lett. vol. 24, no. 5, pp. 339-341, May 2004.
3. M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K. Rim, "Six band k.p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain and silicon thickness," J. Appl. Phys., vol. 94, no. 2, pp. 1079-1095, Jul. 15, 2003.
4. L. Chang, M. Ieong, and M. Yang, "CMOS circuit performance enhancement by surface orientation optimization," IEEE Trans. Electron Devices vol. 51, no. 10, pp. 1621-1627, Oct. 2004.
5. M. Yang, V. Chan, S. H. Ku, M. Ieong, L. Shi, K. K. Chan, C. S. Murthy, R. T. Mo, H. S. Yang, E. A. Lehnef, Y. Surprid, F. F. Jamin, P. Oldiges, Y. Zhang, B. N. To, J. R. Holt, S. E. Steen, M. P. Chudzik, D. M. Fried, K. Bemstein, H. Zhu, C. Y. Sung, J. A. Ott, D. C. Boyd, and N. Rovedo, "On the integration of CMOS with hybrid crystal orientations," in Proc. Symp. VLSI Technol. Dig. Tech. Papers, pp. 160-161.
6. M. Yang, K. Chan, A. Kumar, S.-H. Lo, J. Sleight, L. Chang, R. Rao, S. Bedell, A. Ray, J. Ott, J. Patel, C. D'Emic, J. Rubino, Y. Zhang, L. Shi, S. Steen, E. Sikorski, J. Newbury, R. Meyer, B. To, P. Kozlowski, W. Graham, S. Maurer, S. Medd, D. Canaperi, L. Deligianni, J. Tornello, G. Gibson, T. Dalton, M. Ieong, and G. Shahidi, "Silicon-on-insulator MOSFETs with hybrid crystal orientations," in VLSI Symp. Tech. Dig. 2006, pp. 131-132.
7. K. L. Saenger, J. P. de Souza, K. E. Fogel, J. A. Ott, A. Reznicek, C. Y. Sung, D. K. Sadana, and H. Yin, "Amorphization/templated recrystallization method for changing the orientation of singlecrystal silicon: An alternative approach to hybrid orientation substrates," Appl. Phys. Lett., vol. 87, no. 22, pp. 221 911-1-221 911-3, Nov. 2005.
8. C. Y. Sung, H. Yin, H. Ng, K. L. Saenger, V. Chan, S. Crowder, J. Li, J. A. Ott, R. Bendernage, J. Kempisty, V. Ku, H. K. Lee, Z. J. Luo, A. Madan, R. T. Mo, P. Nguyen, G. Pfeiffer, M. Raccioppo, N. Rovedo, D. K. Sadana, J. P. de Souza, R. Zhang, Z. Ren, and C. Wann, "High performance CMOS bulk technology using direct silicon bond (DSB) mixed crystal orientation substrates," in IEDM Tech. Dig., 2005, pp. 235-238.
9. J. Sullivan, H. R. Kirk, S. Kang, P. J. Ong, and F. J. Henley, "Layer-transfer process modifications for fabricating hybrid crystal orientation engineered substrates," in Proc. IEEE Int. SOI Conf., 2005, pp. 121-122.
10. H. S. Momose et al., "Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide," in VLSI Symp. Tech. Dig., 2001, pp. 77-78.
11. S. Zafar et al., "A comparative study of NBTI as a function of Si substrate orientation and gate dielectrics (SiON and SiON/HfO2)," in Proc. IEEE VLSI-TSA Symp., 2005, pp. 128-129.
12. J. S. Suehle et al., "Ultra-thin gate oxide reliability: Physical model, statistics, and characterization," IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 958-971, Jun. 2002.