Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue TECHNOLOGY SYMP., 2001, Pages 77-78

  Momose, H S ^a   Ohguro, T ^a   Nakamura, S ^a   Toyoshima, Y ^a   Ishiuchi, H ^a   Iwai, H ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTAL ORIENTATION; ELECTRIC BREAKDOWN OF SOLIDS; ELECTRON TUNNELING; INTERFACES (MATERIALS); LEAKAGE CURRENTS; MOSFET DEVICES; OXIDATION; QUALITY CONTROL; SILICA; SURFACE ROUGHNESS; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

DIRECT-TUNNELING GATE OXIDES; TUNELLING LEAKAGE CURRENTS; WAFER ORIENTATION DEPENDENCIES;

CMOS INTEGRATED CIRCUITS;

EID: 0034790103     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)