An 18-mW 1.1752-GHz frequency synthesizer with constant bandwidth for DVB-T tuners

IEEE Transactions on Microwave Theory and Techniques

Volumn 57, Issue 4, 2009, Pages 928-937

  Lu, Lei ^a   Chen, Jinghong ^b   Yuan, Lu ^a   Min, Hao ^a   Tang, Zhangwen ^a  

^a FUDAN UNIVERSITY   (China)

^b ANALOG DEVICES INC   (United States)

Author keywords

Frequency synthesizer; Loop bandwidth; Loop gain; Phase noise; Voltage controlled oscillator (VCO) gain; Wideband

Indexed keywords

CHARGE PUMP CURRENTS; CLOSED-LOOP BANDWIDTHS; CMOS PROCESS; CONSTANT BANDWIDTHS; DIE AREAS; DIFFERENTIALLY-TUNED; DIGITAL VIDEO BROADCASTING - TERRESTRIALS; FREQUENCY OFFSETS; FULLY INTEGRATED; IN-BAND PHASE NOISE; LOOP BANDWIDTH; LOOP GAIN; LOOP STABILITIES; MEASURED RESULTS; OUTPUT FREQUENCIES; PHASE ERRORS; SWITCHED CAPACITORS; VOLTAGE-CONTROLLED OSCILLATOR (VCO) GAIN; WIDEBAND;

BANDWIDTH; COMPUTER GRAPHICS; ELECTRIC CONVERTERS; FREQUENCY ALLOCATION; FREQUENCY SYNTHESIZERS; MULTIMEDIA SYSTEMS; PHASE NOISE; TUNERS; VARIABLE FREQUENCY OSCILLATORS;

TELECOMMUNICATION SYSTEMS;

EID: 64749102225     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2009.2014449     Document Type: Conference Paper

References (25)

1. D. Saias, F. Montaudon, E. Andre, F. Ballleul, M. Bely, P. Busson, S. Dedieu, A. Dezzani, A. Moutard, G. Provins, E. Rouat, J. Roux, G. Wagner, and F. Paillardet, "A 0.12 μm CMOS DVB-T tuner," in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2005, pp. 430-431.
2. M. Dawkins, A. P. Burdett, and N. Cowley, "A single-chip tuner for DVB-T," IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1307-1317, Aug. 2003.
3. S. Levantino, C. Samori, A. Bonfanti, S. L. J. Gierkin, A. L. Lacaita, and V. Boccuzzi, "Frequency dependence on bias current in 5-GHz CMOS VCOs: Impact on tuning range and flicker noise upconversion," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1003-1011, Aug. 2002.
4. J. G. Maneatis, J. Kim., I. McClatchie, J. Maxey, and M. Shankaradas, "Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock, generator PLL," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795-1803, Nov. 2003.
5. Y. Akamine, M. Kawabe, K. Hori, T. Okazaki, M. Kasahara, and S. Tanaka, "AS PLL transmitter with a loop-bandwidth calibration system," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 497-506, Feb. 2008.
6. L. Lu, L. Yuan, H. Min, and Z. Tang, "A fully integrated 1.175-to-2 GHz frequency synthesizer with, constant bandwidth for DVB-T applications," in. Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2008, pp. 303-306.
7. M. G. Floyd, Phaselock Techniques, 3rd ed. New York: Wiley, 2005, pp. 12-28.
8. J. Lee and B. Kim, "A low-noise fast-lock phase-locked loop with adaptive bandwidth control," IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1137-1145, Aug. 2000.
9. D. Hauspie, E.-C. Park, and J. Craninckx, "Wideband VCO with simultaneous switching of frequency band, active core, and varactor size," IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1472-1480, Jul. 2007.
10. T. Nakamura, T. Masuda, N. Shiramizu, K. Washio, T. Kitamura, and N. Hayashi, "A wide-tuning-range VCO with small VCO-gain fluctuation for multi-band W-CDMA RFIC," in Proc. Eur. Solid-State Circuits Conf., Sep. 2006, pp. 448-451.
11. T. Y. Lin, T. Y. Yu, L. W. Ke, and G. K. Dehng, "A low-noise VCO with a constant JtVo o for GSM/GPRS/EDGE applications," in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2008, pp. 387-390.
12. H. Lee, J.-K. Cho, K.-S. Lee, I.-C. Hwang, T.-W. Ahn, K.-S. Nah, and B.-H. Park, "A Σ-Δ fractional- N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1164-1169, Jul. 2004.
13. K.-S. Lee, E.-Y. Sung, I.-C. Hwang, and B.-H. Park, "Fast AFC technique using a code estimation and binary search algorithm, for wideband frequency synthesis," in Proc. Eur. Solid-State Circuits Conf., Sep. 2005, pp. 448-451.
14. Z. Tang, J. He, and H. Min, "A low-phase-noise 1-GHz LC VCO differentially tuned by switched step capacitors," in IEEE Asian Solid-State Circuits Conf, Nov. 2005, pp. 409-412.
15. E. Hegazi, H. Sjöland, and A. A. Abidi, "A filtering technique to lower LC oscillator phase noise," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001.
16. P. Andreani and S. Mattisson, "On the use of MOS varactors in RF VCO's," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 905-910, Jun. 2000.
17. m LC VCOs," IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1325-1332, Aug. 2003.
18. S. Cheng, H. Tong, J. Silva-Martinez, and A. I. Karsilayan, "Design and analysis of an ultrahigh-speed glitch-free fully differential charge pump with, minimum output current variation and accurate matching," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 9, pp. 843-847, Sep. 2006.
19. M. Terrovitis, M. Mack, K. Singh, and M. Zargari, "A 3.2 to 4 GHz 0.25 μm CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN," in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2004, pp. 95-96.
20. K. Shu, E. Sánchez-Sinencio, J. Silva-Martínez, and S. Embabi, "A 2.4-GHz monolithic fractional- N frequency synthesizer with robust phase switching prescaler and loop capacitance multiplier," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 866-874, Jun. 2003.
21. C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, "A family of low-power truly modular programmable dividers in standard 0.35- μm CMOS technology," IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1039-1045, Jul. 2000.
22. rms phase-noisering-oscillator-based frequency synthesizer for low-IF single-chip DBS satellite tuner-demodulator SoC," in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 618-619.
23. M. Marutani, H. Anbutsu, M. Kondo, N. Shirai, H. Yamazaki, and Y. Watanabe, "An 18 mW 90 to 770 MHz synthesizer with, agile autotuning for digital TV-tuners," in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 192-193.
24. I. Vassiliou, K. Vavelidis, S. Bouras, S. Kavadias, Y. Kokolakis, G. Kamoulakos, A. Kyranas, C. Kapnlstls, and N. Haralabldls, "A 0.18 μm CMOS dual-band direct-conversion DVB-H receiver," in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 606-607.
25. M. Gupta, S. Lerstaveesin, D. Kang, and B.-S. Song, "A 48-to-860 MHz CMOS direct-conversion TV tuner," in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2007, pp. 206-207.