Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 4, 2007, Pages 427-437

  Luo, Jiong ^b,c   Jha, Niraj K ^a,b   Peh, Li Shiuan ^a,b  

^a IEEE   (United States)

^b Princeton University   (United States)

^c SYNOPSYS INC   (United States)

Author keywords

Distributed systems; Low power; Scheduling; Voltage scaling; Voltage scalable interconnection network

Indexed keywords

BANDWIDTH REQUIREMENTS; DISTRIBUTED SYSTEMS; VOLTAGE SCALABLE INTERCONNECTION NETWORK; VOLTAGE SCALING;

DISTRIBUTED COMPUTER SYSTEMS; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; FREQUENCY ALLOCATION; INTERCONNECTION NETWORKS; PROGRAM PROCESSORS; REAL TIME SYSTEMS;

TELECOMMUNICATION LINKS;

EID: 34247634723     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.893660     Document Type: Article

References (30)

1. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb, "The ALPHA 21364 network architecture," in Proc. Hot Interconnects 9, 2001, p. 113.
2. W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. Design Autom. Conf., 2001, pp. 684-689.
3. L. Benini and G. De Micheli, "Powering networks on chips: Energy-efficient and reliable interconnect design for SoCs," in Proc. Int. Symp. Syst. Synthesis, 2001, pp. 33-38.
4. G. Wei, J. Kim, D. Liu, S. Sidiropoulos, and M. Horowitz, "A variable-frequency parallel I/O interface with adaptive power-supply regulation," J. Solid-State Circuits, vol. 35, no. 11, pp. 1600-1610, Nov. 2000.
5. J. Kim and M. Horowitz, "Adaptive supply serial links with sub-1 V operation and per-pin clock recovery," in Proc. Int. Solid-State Circuits Conf., 2002, pp. 216-217.
6. T. T. Ye, L. Benini, and G. De Micheli, "Analysis of power consumption on switch fabrics in network routers," in Proc. Design Autom. Conf., 2002, pp. 524-529.
7. H. Wang, X. Zhu, L.-S. Peh, and S. Malik, "Orion: A power-performance simulator for interconnection networks," in Proc. Int. Symp. Microarch., 2002, pp. 294-305.
8. J. Liu, P. H. Chou, and N. Bagherzadeh, "Communication speed selection for embedded systems with networked voltage-scalable processors," in Proc. Hardw./Softw. Co-Des. Wkshp., 2002, pp. 169-174.
9. L. Shang, L.-S. Peh, and N. K. Jha, "Dynamic voltage scaling with links for power optimization of interconnection networks," in Proc. High-Performance Comput. Arch. Symp., 2003, pp. 91-102.
10. F. Yao, A. Demers, and S. Shenker, "A scheduling model for reduced CPU energy," in Proc. Symp. Foundations Comput. Sci., 1995, pp. 374-382.
11. A. Manzak and C. Chakrabarti, "Variable voltage task scheduling algorithms for minimizing energy," in Proc. Int. Symp. Low Power Electron. Des., 2001, pp. 279-282.
12. T. Pering, T. Burd, and R. Brodersen, "The simulation and evaluation of dynamic voltage scaling algorithms," in Proc. Int. Symp. Low Power Electron. Des., 1998, pp. 76-81.
13. F. Gruian and K. Kuchcinski, "LEneS : Task-scheduling for low-energy systems using variable voltage processors," in Proc. Asian South Pacific Des. Autom. Conf., 2001, pp. 449-455.
14. J. Luo and N. K. Jha, "Static and dynamic variable voltage scheduling algorithms for real-time heterogeneous distributed embedded systems," in Proc. Asian South Pacific Des. Autom. Conf., 2002, pp. 719-724.
15. Y. Zhang, X. Hu, and D. Chen, "Task scheduling and voltage selection for energy minimization," in Proc. Des. Autom. Conf., 2002, pp. 183-188.
16. S. Raje and M. Sarrafzadeh, "Scheduling with multiple voltages," VLSI J. Integr., vol. 23, no. 1, pp. 37-59, Oct. 1997.
17. P. Eles, K. Kuchcinski, Z. Peng, and A. Doboli, "Scheduling of conditional process graphs for the synthesis of embedded systems," in Proc. Des., Autom. Test Eur. Conf., 1998, pp. 132-138.
18. Y. Xie and W. Wolf, "Allocation and scheduling of conditional task graph in co-synthesis," in Proc. Des. Autom. Test Eur. Conf., 2001, pp. 620-625.
19. D. Ziegenbein, K. Richter, R. Ernst, J. Teich, and L. Thiele, "Representation of process mode correlation for scheduling," in Proc. Int. Conf. Comput.-Aided Des., 1998, pp. 54-61.
20. B. Caminero, F. Quiles, J. Duato, D. Love, and S. Yalamanchili, "Performance evaluation of the MMR using MPEG-2 video traces," in Proc. Workshop Commun., Arch. Appl. Netw. Based Parallel Comput., 1999, pp. 62-76.
21. S. Balakrishnan and F. Ozguner, "A priority-driven flow control mechanism for real-time traffic in multiprocessor networks," IEEE Trans. Parallel Distrib. Syst., vol. 9, no. 7, pp. 664-678, Jul. 1998.
22. P. T. Gaughan and S. Yalamanchili, "A family of fault-tolerant routing protocols for direct multiprocessor networks," IEEE Trans. Parallel Distrib. Syst., vol. 6, no. 5, pp. 482-497, May 1995.
23. W. Lee, R. Barua, M. Frank, D. Srikrishna, J. Babb, V. Sarkar, and S. Amarasinghe, "Space-time scheduling of instruction-level parallelism on a RAW machine," in Proc. Int. Conf. Arch. Support Program. Lang. Operat. Syst., 1998, pp. 4-7.
24. K. S. Vallerio and N. K. Jha, "Task graph extraction for embedded system synthesis," in Proc. Int. Conf. VLSI Des., 2003, pp. 480-485.
25. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.
26. Y. Kwok and I. Ahmad, "Dynamic critical-path scheduling: An effective technique for allocating task graphs to multiprocessors," IEEE Trans. Parallel Distr. Syst., vol. 7, no. 5, pp. 506-521, May 1996.
27. C. M. Woodside and G. G. Monforton, "Fast allocation of processes in distributed and parallel systems," IEEE Trans. Parallel Distr. Syst., vol. 4, no. 2, pp. 164-174, Feb. 1993.
28. T. Lv, B. Ozer, and W. Wolf, "Workload characterization for smart cameras," presented at the Media Streaming Process., Austin, TX, 2001.
29. R. P. Dick and N. K. Jha, "MOCSYN: Multiobjective core-based single-chip system synthesis," in Proc. Des., Autom. Test Eur. Conf., 1999, pp. 263-270.
30. _, "CORDS: Hardware-software co-synthesis of reconfigurable real-time distributed embedded systems," in Proc. Int. Conf. Comput.-Aided Des., 1998, pp. 62-68.