Quasi-2D compact modeling for double-gate MOSFET

2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004

Volumn 2, Issue , 2004, Pages 108-113

  Chan, Mansun ^a   Man, Tze Yin ^a   He, Jin ^b   Xi, Xuemei ^b   Lin, Chung Hsun ^b   Lin, Xinnan ^a   Ko, Ping K ^a   Niknejad, Ali M ^b   Hu, Chenming ^c  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

BSIM; Circuit Simulation; CMOS Device; Device model; Double gate MOSFET; SPICE

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; GATES (TRANSISTOR); QUANTUM EFFICIENCY; SILICON; THICKNESS CONTROL; THIN FILMS;

BSIM; CIRCUIT SIMULATION; DEVICE MODEL; DOUBLE-GATE MOSFET; SPICE;

MOSFET DEVICES;

EID: 6344280362     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. D. Frank, S. Laux, and M. Fischetti, "Monte Carlo Simulation of a 30-nm Dual-Gate MOSFET: How Far Can Silicon Go?" in IEDM Tech. Dig., 1992, pp. 553
2. J. R. Brews, "A Charge Sheet Model of the MOSFET," Solid-Stale Electron, issue 21, 345 (1978).
3. J. He, X. Xi, M. Chan, A. Niknejad, and C. Hu, "An Advanced Surface-Potential-Plus MOSFET Model", Technical Proceedings of the 2003 Nanotechnology Conference, pp. 262-665, February 23-27, 2003, San Francisco, California, USA.
4. J. He, X. Xi, C.-H. Lin, M. Chan, A. Niknejad, and C. Hu, "A Non-Charge-Sheet Analytic Theory for Undoped Symmetric Double-Gate MOSFETs from the Exact Solution of Poisson's Equation using SPP Approach", Technical Proceedings of the 2004 Nanotechnohgy Conference
5. M. Ieong, E. C. Jones, T. Kanarsky, Z. Ren, O. Dokumaci, R. A. Roy, L. Shi, T. Furukawa, Y. Taur, R. J. Miller, and H.-S.P. Wong, "Experimental evaluation of carrier transport and device design for planar symmetric/ asymmetric double-gate/ground-plane CMOSFETs," IEDM Tech. Dig., pp. 19.6.1-19.6.4, 2001
6. D. Esseni, A. Abramo, L. Selmi, and E. Sangiorgi, "Study of low field electron transport in ultra-thin single and double-gate SOI MOSFETs," IEDM Tech. Dig., pp. 719-722, 2002.
7. K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S. Takagi, "Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm," IEDM Tech. Dig., pp. 47-50, 2002.
8. K. Uchida, J. Koga, R. Ohba, T. Numata, and S. Takagi, "Experimental evidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance, and threshold voltage of ultrathin body SOI MOSFETs," IEDM Tech. Dig., pp. 29.4.1 -29.4.4, 2001.
9. D. Esseni, M. Mastrapasqua, G. K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, "An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode," IEEE Trans. Electron Devices, Vol. 50, No. 3, pp. 802-808, 2003.
10. M. Shoji, and S. Horiguchi, "Electronic structures and phonon limited electron mobility of double-gate silicon-on-insulator Si inversion layers," J. Appl Phys., vol. 85, no. 5, pp. 2722-2731, 1999.
11. M. S. Liang, J. Y. Choi, P. K. Ko, and C. Hu, "Inversion-Layer Capacitance and Mobility of Very Thin Gate-Oxide MOSFET's," IEEE Trans. Electron Devices, ED-33, pp. 409, 1986.
12. Y. A. El Mansy and A. R. Boothroyd, "A simple two-dimensional model for IGFET operation in the saturation region," IEEE Transactions on Electron Devices, Vol. 24, No. 3, pp. 254-262, 1977.
13. P. K. Ko, R. S. Muller and C. Hu, "A unified model for hot-electron currents in MOSFETs," IEDM Tech. Dig., 1981, p. 600.
14. Y. Taur, "Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs," IEEE Transactions on Electron Devices, Vol. 48, No. 12, pp. 2861-2869, 2001
15. K. W. Terrill, C. Hu, P. K. Ko, "An Analytical Model for the Channel Electric Field in MOSFET's with Graded-Drain Structures," IEEE Electron Device Letter, Vol. 5, No. 11.pp.440-442, 1984
16. P. Su, K. Goto, T. Sugii and C. Hu, "A Thermal Activation view of Low Voltage Impact Ionization in MOSFETs", IEEE Electron Device Letters, Vol. 23, no. 9, pp. 550-552, September 2002