Design optimization of NEMS switches for suspended-gate single-electron transistor applications

IEEE Transactions on Nanotechnology

Volumn 8, Issue 2, 2009, Pages 174-184

  Pruvost, Benjamin ^a   Uchida, Ken ^a,b   Mizuta, Hiroshi ^a,b,c   Oda, Shunri ^a,b  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

^c UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

1 D and 3 D modeling; Cantilever switch; Movable gate; Nanoelectromechanical system (NEMS); Single electron transistor (SET)

Indexed keywords

APPLICATIONS; ATOMIC FORCE MICROSCOPY; CAPACITANCE MEASUREMENT; ELECTRONS; NANOCANTILEVERS; NEMS; SWITCHES; THREE DIMENSIONAL COMPUTER GRAPHICS; TRANSIENTS; TRANSISTORS;

1-D AND 3-D MODELING; CANTILEVER SWITCH; MOVABLE GATE; NANOELECTROMECHANICAL SYSTEM (NEMS); SINGLE-ELECTRON TRANSISTOR (SET);

THREE DIMENSIONAL;

EID: 62449219254     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2008.2010453     Document Type: Article

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