Design considerations for complementary nanoelectromechanical logic gates

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 299-302

  Akarvardar, K ^a   Elata, D ^a   Parsa, R ^a   Wan, G C ^a   Yoo, K ^a   Provine, J ^a   Peumans, P ^a   Howe, R T ^a   Wong, H S P ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; LOGIC DEVICES; METALS; NEMS; NONMETALS; PHOTOELECTRIC RELAYS; PHOTORESISTS; SILICON;

DESIGN CONSIDERATIONS; LOW-DENSITY MATERIALS; MEMS RELAYS; ORDERS-OF-MAGNITUDE; PULL-IN; SWITCHING ENERGY;

LOGIC GATES;

EID: 50249113248     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418930     Document Type: Conference Paper

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