A simple latency tolerant processor

26th IEEE International Conference on Computer Design 2008, ICCD

Volumn , Issue , 2008, Pages 384-389

  Nekkalapu, Satyanarayana ^b   Akkary, Haitham ^a   Jothi, Komal ^b   Retnamma, Renjith ^b   Xiaoyu, Song ^b  

^a AMERICAN UNIVERSITY OF BEIRUT   (Lebanon)

^b PORTLAND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; MEMORY ARCHITECTURE; PROGRAM PROCESSORS;

DYNAMIC SCHEDULERS; LONG-LATENCY CACHE; MULTI-CORE PROCESSOR; OUT-OF-ORDER EXECUTION; PARALLEL APPLICATION; SINGLE-THREAD PERFORMANCE; SUPERSCALAR ARCHITECTURE; TOLERANT ARCHITECTURES;

CACHE MEMORY;

EID: 62349140492     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751889     Document Type: Conference Paper

References (26)

1. H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. MICRO-36, December 2003.
2. R. D. Barnes, E. M. Nystrom, J. W. Sios, S. J. Patel, N. Navarro, and W. W. Hwu. Beating In-Order Stalls with "Flea Flicker" Two-Pass Pipelining. MICRO-36, December 2003.
3. R. D. Barnes, S. Ryoo, W. W. Hwu. "Flea Flicker" Multi-Pass Pipelining: An Alternative to the High power Out-of-Order Offence. MICRO-38, November 2005.
4. R. Chappell, J. Stark, S. Kim, S. Reinhardt, and Y. Patt. Simultaneous Subordinate Multithreading (SSMT). ISCA-26, May 1999.
5. S. Chaudhry, P. Caprioli, S. Yip, M. Tremblay. "High-performance Throughput Computing." IEEE Micro, vol. 25, no. 3, pp. 32-45, May 2005.
6. A. Cristal, D. Ortega, J. Llosa, and M. Valero. Out-of-Order Commit Processors. HPCA-10, February 2004.
7. A. Cristal, O. J. Santana, F. Gazorla, M. Galluzzi, T. Ramirez, M. Pericas, and M. Valero. Kilo-Instruction Processors: Overcoming the Memory Wall. In IEEE MICRO, vol. 25, no. 3, May/June 2005.
8. A. Cristal, M. Valero, J. Llosa, and A. Gonzalez. Large Virtual ROBs by Processor Checkpointing. Tech. Report, UPC-DAC-2002-39, Department of Computer Science, Barcelona, Spain, July 2002.
9. J. Dundas and T. Mudge. Improving data cache performance by preexecuting instructions under a cache miss. In Proceedings of the International Conference on Supercomputing, June 1997.
10. First the Tick, Now the Tock: Next Generation Intel Microarchitecture (Nehalem). Intel Corporation White Paper. http://www.intel.com/pressroom/ archive/reference/whitepaper-nehale m.pdf
11. A. Gandhi, H. Akkary, R. Rajwar, S. T. Srinivasan and K. Lai. Scalable Load and Store Processing in Latency Tolerant Processors. ISCA-32, June 2005.
12. J. Held, J. Bautista, and S. Koehl. From a Few Cores to Many: A Tera-Scale Computing Research Review. Intel Research White Paper. http://download.intel.com/research/platform/terascale/terascale-overview-paper. pdf.
13. T. Karkhanis and J. E. Smith. A Day in the Life of a Data Cache Miss. In Workshop on Memory Performance Issues, June 2002.
14. A. R. Lebeck, J. Koppanalil, T. Li, J. Patwardhan, and E. Rotenberg. A large, fast instruction window for tolerating cache misses. ISCA-29, May 2002.
15. J. F. Martinez, J. Renau, M. C. Huang, M. Prvulovic, and J. Torrellas. Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors. MICRO-35, November 2002.
16. A.Moshovos, S. Breach, T. Vijaykumar, and G. Sohi. Dynamic Speculation and Synchronization of Data Dependences. ISCA-24, June 1997.
17. O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. HPCA-9, February 2003.
18. D. B. Papworth. Tuning the Pentium Pro Microarchitecture. In IEEE MICRO, vol. 16, no. 2, April 1996.
19. A. Roth and G. S. Sohi. Speculative Data-Driven Multi-Threading. HPCA-7, January 2001.
20. Y. Song and M. Dubois, Assisted Execution. University of Southern California, Technical Report #CENG 98-25, Department of EESystems, October 1998.
21. S. T. Srinivasan, H. Akkary, T. Holman, and K. Lai. A Minimal Dual- Core Speculative Multithreading Architecture. In Proceedings of the 22nd IEEE International Conference on Computer Design, October 2004.
22. S. T. Srinivasan, R. Rajwar, H. Akkary, A. Gandhi, and M. Upton. Continual Flow Pipelines. ISCA-11, October 2004.
23. M. Tremblay and S. Chaudhry. A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC Processor. In Proceedings of IEEE International Solid-State Circuits Conference, February 2008.
24. W. Wulf and S. McKee. Hitting the Memory Wall: Implications of the Obvious. ACM SIGArch Computer Architecture News, 23(1):20-24, March 1995.
25. X86 Cycle Accurate Processor Simulation Design Infrastructure. http://www.ptlsim.org/
26. C. B. Zilles and G. S. Sohi. Execution-based prediction using speculative slices. ISCA-28, June 2001.