Key research issues for reconfigurable network-on-chip

Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008

Volumn , Issue , 2008, Pages 181-186

  Dafali, R ^a   Diguet, J Ph ^a   Sevaux, M ^a  

^a UNIVERSITÉ EUROPÉENNE DE BRETAGNE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH REQUIREMENTS; CURRENT SITUATIONS; DESIGN PARADIGMS; DYNAMIC BEHAVIORS; DYNAMIC RECONFIGURATIONS; NETWORK INFRASTRUCTURES; NETWORK ON CHIPS; RE-CONFIGURABLE; RE-USABLE DESIGNS; RECONFIGURABLE NETWORKS; RESEARCH ISSUES; SCALABLE SYSTEMS;

DISTRIBUTED COMPUTER SYSTEMS; DYNAMIC MODELS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS;

ELECTRIC NETWORK TOPOLOGY;

EID: 62349100887     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ReConFig.2008.72     Document Type: Conference Paper

References (19)

1. Arteris. A comparison of network-on-chip and busses. White paper., 2005.
2. L. Benini and G. De Micheli. Powering networks on chips. System Synthesis, 2001. Proceedings. The 14th International Symposium on, pages 33-38, 2001.
3. T. Bjerregaard and S. Mahadevan. A survey of research and practices of network-on-chip. ACM Computing Surveys, 38, 2006.
4. C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J. van der Veen. Dynoc: A dynamic infrastructure for communication in dynamically reconfugurable devices. Int. Conf. on Field Programmable Logic and Applications, Aug. 2005.
5. L. Braun, M. Hubner, J. Becker, T. Perschke, V. Schatz, and S. Bach. Circuit switched run-time adaptive network-on-chip for image processing applications. Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on, pages 688-691, Aug. 2007.
6. C. Francalanci and P. Giacomazzi. High-performance self-routing algorithm for multiprocessor systems with shuffle interconnections. Parallel and Distributed Systems, IEEE Transactions on, 17(1):38-50, Jan. 2006.
7. A. Hansson, M. Coenen, and K. Goossens. Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. Design, Automation, Test in Europe Conference and Exhibition, 2007. DATE '07, pages 1-6, April 2007.
8. J-Ph. Diguet, S. Evain, R. Vaslin, G. Gogniat, and E. Juin. Noccentric security of reconfigurable soc. In 1st ACM/IEEE Int. Symp. on Networks-on-Chips, Princeton, USA, may 2007.
9. J. Kramer and J. Magee. Dynamic configuration for distributed systems. IEEE Transactions on Software Engineering, 11(4):424-436, April 1985.
10. Jeff Kramer and Jeff Magee. The evolving philosophers problem: Dynamic change management. IEEE Trans. Softw. Eng., 16(11):1293-1306, 1990.
11. T. Marescaux, B. Bricke, P. Debacker, V. Nollet, and H. Corporaal. Dynamic time-slot allocation for qos enabled networks on chip. Embedded Systems for Real-Time Multimedia, 2005. 3rd Workshop on, pages 47-52, Sept. 2005.
12. H. Moussa, A. Baghdadi, and M. Jezequel. Binary de bruijn on-chip network for a flexible multiprocessor ldpc decoder. Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, pages 429-434, June 2008.
13. C.A. Nicopoulos, Dongkook Park, Jongman Kim, N. Vijaykrishnan, M.S. Yousif, and C.R. Das. Vichar: A dynamic virtual channel regulator for network-on-chip routers. Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International Symposium on, pages 333-346, Dec. 2006.
14. V. Nollet, T. Marescaux, P. Avasare, D. Verkest, and J.-Y. Mignolet. Centralized run-time resource management in a network-on-chip containing reconfigurable hardware tiles. Design, Automation and Test in Europe, 2005. Proceedings, pages 234-239 Vol. 1, March 2005.
15. Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, and Serge Vernalde. Operating-system controlled network on chip. In DAC '04: Proceedings of the 41st annual conference on Design automation, pages 256-259, New York, NY, USA, 2004. ACM.
16. Thilo Pionteck, Roman Koch, and Carsten Albrecht. Applying partial reconfiguration to networks-on-chips. In FPL, pages 1-6, 2006.
17. A. Radulescu, J. Dielissen, K. Goossens, E. Rijpkema, and Paul Wielage. An efficient on-chip ni offering guaranteed services, shared-memory abstraction, and flexible network configuration. In IEEE TCAD, 2004.
18. S. Evain and J-Ph. Diguet. Efficient space-time noc path allocation based on mutual exclusion and pre-reservation. In 17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Italy, mar 2007.
19. M.B. Stensgaard and J. Sparso. Renoc: A network-on-chip architecture with reconfigurable topology. Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium on, pages 55-64, April 2008.