Circuit switched run-time adaptive Network-on-Chip for image processing applications

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2007, Pages 688-691

  Braun, Lars ^a   Hübner, Michael ^a   Becker, Jürgen ^a   Perschke, Thomas ^b   Schatz, Volker ^b   Bach, Stefan ^b  

^a UNIVERSITY OF KARLSRUHE   (Germany)

^b FRAUNHOFER IOSB   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS; COBALT; COMMUNICATION SYSTEMS; COMPUTER SOFTWARE REUSABILITY; DIGITAL IMAGE STORAGE; ELECTRIC NETWORK TOPOLOGY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; IMAGING SYSTEMS; INTERNET PROTOCOLS; NETWORK ARCHITECTURE;

ADAPTIVE CIRCUITS; ADAPTIVITY; BUS-BASED; CIRCUIT SWITCHED; ELECTRONIC SYSTEMS; FUNCTIONAL BLOCKS; HETEROGENEOUS PLATFORMS; IMAGE PROCESSING APPLICATIONS; PARTIAL RECONFIGURATIONS; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARES; RESEARCH GROUPS; RUN-TIME RECONFIGURATIONS; SCALABLE COMMUNICATIONS; SILICON DIES; SOFTWARE PARTS; XILINX VIRTEX;

SWITCHING CIRCUITS;

EID: 48149106743     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380746     Document Type: Conference Paper

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