Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect

Microsystem Technologies

Volumn 15, Issue 5, 2009, Pages 677-686

  Choa, Sung Hoon ^a  

^a Seoul National University of Science and Technology   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CLEANING; COPPER; ELECTRIC CONNECTORS; ELECTROCHEMISTRY; MEMS; MICROELECTROMECHANICAL DEVICES; PACKAGING; RELIABILITY; SHEAR STRENGTH; TESTING; THERMAL EXPANSION; TIN;

ADHESION PERFORMANCE; BONDING INTERFACES; BONDING TECHNOLOGIES; CLEANING PROCESS; COPPER DIFFUSIONS; CU DIFFUSIONS; DESIGN CONSIDERATIONS; ELECTRICAL CONNECTIONS; ELECTROPLATED COPPERS; ELECTROPLATING PROCESS; ETCH PROFILES; EUTECTIC BONDINGS; FABRICATION PROCESS; HERMETIC SEALING; HERMETICITY; LOW TEMPERATURES; MECHANICAL EFFECTS; MEMS DEVICES; MEMS PACKAGES; MEMS PACKAGING; METALLIZATION; PLASMA ASHING; RELIABILITY TESTS; SHEAR STRENGTH TESTS; SQUARE LOOPS; THERMAL EXPANSION MISMATCHES; THROUGH HOLES; THROUGH-VIAS; VIA HOLES; VOID-FREE; WAFER INTERCONNECTIONS; WAFER LEVELS; WAFER-LEVEL PACKAGING;

WAFER BONDING;

EID: 62249104417     PISSN: 09467076     EISSN: None     Source Type: Journal    
DOI: 10.1007/s00542-009-0788-3     Document Type: Article

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