On wire failures in microelectronic packages

IEEE Transactions on Device and Materials Reliability

Volumn 9, Issue 1, 2009, Pages 2-8

  Van Driel, Willem D ^a,b   Van Silfhout, Richard B R ^c   Zhang, G Q ^a,b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Delamination; Finite element (FE) modeling; Wire bond reliability; Wire loop shape

Indexed keywords

DELAMINATION; ELECTRONICS PACKAGING; MICROELECTRONICS; RELIABILITY; STEEL SHEET;

ELECTRONIC PACKAGES; FE MODELS; FINITE ELEMENTS; FINITE-ELEMENT (FE) MODELING; MATERIAL CHANGES; MICRO-ELECTRONIC PACKAGES; MODE INTERACTIONS; NON-LINEAR BEHAVIORS; PREDICTIVE MODELING; SIMULATION-BASED OPTIMIZATIONS; TESTING ENVIRONMENTS; THERMO-MECHANICAL BEHAVIORS; WIRE FAILURES; WIRE-BOND RELIABILITY;

WIRE;

EID: 61849104505     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2008.2002343     Document Type: Article

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