Prediction of interfacial delamination in stacked IC structures using combined experimental and simulation methods

Microelectronics Reliability

Volumn 44, Issue 12, 2004, Pages 2019-2027

  Van Driel, W D ^a   Liu, C J ^b   Zhang, G Q ^c   Janssen, J H J ^a   Van Silfhout, R B R ^c   Van Gils, M A J ^c   Ernst, L J ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DELAMINATION; FINITE ELEMENT METHOD; PASSIVATION; SILICON WAFERS; STACKING FAULTS; STRESS CONCENTRATION; TENSILE TESTING; THERMAL EXPANSION; THERMAL LOAD;

PACKAGE STRUCTURES; PASSIVATION LAYERS; STRESS COMPONENTS;

INTEGRATED CIRCUITS;

EID: 6344254955     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.05.002     Document Type: Conference Paper

References (12)

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