Reliability of wire bonding on low-k dielectric material in damascene copper integrated circuits PBGA assembly

Microelectronics Reliability

Volumn 42, Issue 9-11, 2002, Pages 1535-1540

  Sivakumar, Mohandass ^a   Kripesh, Vaidyanathan ^a   Choong, Chong Ser ^a   Chong, Chai Tai ^a   Lim, Loon Aik ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b ASM Singpaore Pte Ltd   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CLEANING; COPPER; INTEGRATED CIRCUITS; LOW-K DIELECTRIC; OPTIMIZATION; RELIABILITY; RELIABILITY ANALYSIS; TIMING CIRCUITS; WIRE;

CHIP STRUCTURES; CLEANING PROCESS; CONDUCTOR MATERIALS; CU METALLIZATION; DAMASCENE COPPER; ELECTRICAL RESISTANCES; FEATURE SCALING; RELIABILITY PERFORMANCE;

DIELECTRIC MATERIALS;

EID: 3843131023     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(02)00185-3     Document Type: Conference Paper

References (6)

1. International Technology Roadmap for Semiconductor 2001 edition.
2. Andrew et al, "A Method of Investigating Fine Shorting Whiskers Within a Leadframe Molded Package", IEEE Transaction on Advanced Packaging, Vol 24, No 1, Feb 2001, pp 99-103.
3. Lowry et al, US Patent 6,054,012.
4. M. Sivakumar et al, "Process Development & Characterization for Oxide Removal and Cleaning of Cu metallized Chips for Wire Bonding Applications" Advanced Packaging Technologies 1, Semicon Singapore 2002, pp 171-177.
5. th International Symposium on Microelectronics (IMAPS-2001) 2001 Balitmore, US, pp 484-490
6. V. Kripesh et al, "Wire bonding Process Impact on Low-K dielectric Material in Damascene Copper Integrated Circuits": Proceedings of ECTC 2002, San Diego, pp 873-880. (Pubitemid 34692051)