Design and evaluation of mixed 3T-4T FinFET stacks for leakage reduction

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5349 LNCS, Issue , 2009, Pages 31-41

  Agostinelli, Matteo ^a   Alioto, Massimo ^b   Esseni, David ^a   Selmi, Luca ^a  

^a UNIVERSITY OF UDINE   (Italy)

^b UNIVERSITY OF SIENA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; TIME MEASUREMENT;

4T-FINFET; ANALYTICAL RESULTS; BULK TECHNOLOGIES; CLOSED FORMS; DESIGN CRITERION; FIGURE OF MERITS; LEAKAGE MODELS; LEAKAGE REDUCTIONS; ORDERS OF MAGNITUDES; TRANSISTOR STACKS;

TIMING CIRCUITS;

EID: 61649111219     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-95948-9_4     Document Type: Conference Paper

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