메뉴 건너뛰기




Volumn 52, Issue 12, 2005, Pages 2609-2615

NBTI degradation and its impact for analog circuit reliability

Author keywords

Analog mixed signal circuits; Circuit lifetime; Negative bias temperature instability (NBTI); PMOSFET degradation; Threshold voltage shift

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPUTER SIMULATION; DIGITAL TO ANALOG CONVERSION; ELECTRIC CURRENTS; MOSFET DEVICES; OPERATIONAL AMPLIFIERS; RELIABILITY; THRESHOLD VOLTAGE;

EID: 29244437184     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.859570     Document Type: Article
Times cited : (89)

References (29)
  • 1
    • 0032633963 scopus 로고    scopus 로고
    • "Bias temperature instability in scaled p+ polysilicon gate p-MOSFETs"
    • May
    • Y. Yamamoto, K. Uwasawa, and T. Mogami, "Bias temperature instability in scaled p+ polysilicon gate p-MOSFETs," IEEE Trans. Electron Devices, vol. 46, no. 5, pp. 921-926, May 1999.
    • (1999) IEEE Trans. Electron Devices , vol.46 , Issue.5 , pp. 921-926
    • Yamamoto, Y.1    Uwasawa, K.2    Mogami, T.3
  • 2
    • 0033280060 scopus 로고    scopus 로고
    • "Impact for bias-temperature stability for direct tunneling ultrathin gate oxide on MOSFET scaling"
    • N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, "Impact for bias-temperature stability for direct tunneling ultrathin gate oxide on MOSFET scaling," in VLSI Symp. Tech. Dig., 1999, pp. 73-74.
    • (1999) VLSI Symp. Tech. Dig. , pp. 73-74
    • Kimizuka, N.1    Yamamoto, T.2    Mogami, T.3    Yamaguchi, K.4    Imai, K.5    Horiuchi, T.6
  • 5
    • 0842288185 scopus 로고    scopus 로고
    • "Effect of pMOST bias-temperature instability on circuit reliability performance"
    • Y.-H. Lee, N. Mielke, B. Sabi, S. Stadler, R. Nachman, and S. Hu, "Effect of pMOST bias-temperature instability on circuit reliability performance," in IEDM Tech. Dig., 2003, pp. 353-356.
    • (2003) IEDM Tech. Dig. , pp. 353-356
    • Lee, Y.-H.1    Mielke, N.2    Sabi, B.3    Stadler, S.4    Nachman, R.5    Hu, S.6
  • 6
    • 0041340533 scopus 로고    scopus 로고
    • "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing"
    • Jul
    • D. Schroder and J. F. Bobcock, "Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing," J. Appl. Phys., vol. 94, pp. 1-18, Jul. 2003.
    • (2003) J. Appl. Phys. , vol.94 , pp. 1-18
    • Schroder, D.1    Bobcock, J.F.2
  • 7
    • 18144399347 scopus 로고    scopus 로고
    • "Impact of negative bias temperature instability on product parametric drift"
    • V. Reddy, J. Carulli, A. Krishnan, W. Bosch, and B. Burgess, "Impact of negative bias temperature instability on product parametric drift," in Proc. Int. Test Conf., 2004, pp. 148-155.
    • (2004) Proc. Int. Test Conf. , pp. 148-155
    • Reddy, V.1    Carulli, J.2    Krishnan, A.3    Bosch, W.4    Burgess, B.5
  • 8
    • 10044256253 scopus 로고    scopus 로고
    • "Impact of NBTI and HCI on ProOSFET threshold voltage drift"
    • P. Chaparala and D. Brisbin, "Impact of NBTI and HCI on ProOSFET threshold voltage drift," Microelectron. Reliab., vol.45, pp. 13-18, 2005.
    • (2005) Microelectron. Reliab. , vol.45 , pp. 13-18
    • Chaparala, P.1    Brisbin, D.2
  • 13
    • 0035714856 scopus 로고    scopus 로고
    • "SoC CMOS technology for NBTI/CHC immune I/O and analog circuits implementing surface and buried channel structures"
    • Y. Nishida, H. Sayama, K. Ohta, H. Oda, M. Katayama, Y. Inoue, H. Morimoto, and M. Inuishi, "SoC CMOS technology for NBTI/CHC immune I/O and analog circuits implementing surface and buried channel structures," in IEDM Tech. Dig., 2001, pp. 869-872.
    • (2001) IEDM Tech. Dig. , pp. 869-872
    • Nishida, Y.1    Sayama, H.2    Ohta, K.3    Oda, H.4    Katayama, M.5    Inoue, Y.6    Morimoto, H.7    Inuishi, M.8
  • 14
    • 0017493207 scopus 로고
    • "Negative bias stress of MOS devices at high electric fields and degradation of MOS devices"
    • K. O. Jeppson and C. M. Svensson, "Negative bias stress of MOS devices at high electric fields and degradation of MOS devices," J. Appl. Phys., vol. 48, pp. 2004-2016, 1977.
    • (1977) J. Appl. Phys. , vol.48 , pp. 2004-2016
    • Jeppson, K.O.1    Svensson, C.M.2
  • 15
    • 36449005547 scopus 로고
    • "Mechanism of negative-bias-temperature instability"
    • C. Blat, E. Nicollian, and E. Poindexter, "Mechanism of negative-bias-temperature instability," J. Appl. Phys., vol. 69, no. 3, pp. 1712-1720, 1991.
    • (1991) J. Appl. Phys. , vol.69 , Issue.3 , pp. 1712-1720
    • Blat, C.1    Nicollian, E.2    Poindexter, E.3
  • 16
    • 0000005489 scopus 로고
    • "Generalized diffusion-reaction model for the low-field charge build up instability at the $Si-SiO_2$ interface"
    • S. Ogawa and N. Shiono, "Generalized diffusion-reaction model for the low-field charge build up instability at the $Si-SiO_2$ interface," Phys. Rev. B, Condens. Matter, vol. 51, no. 7, pp. 4218-4230, 1995.
    • (1995) Phys. Rev. B, Condens. Matter , vol.51 , Issue.7 , pp. 4218-4230
    • Ogawa, S.1    Shiono, N.2
  • 17
    • 36449000462 scopus 로고
    • "Interface-trap generation at ultrathin $SiO_2$ (4-6 nm)-Si interfaces during negative-bias temperature aging"
    • S. Ogawa, M. Shimaya, and N. Shiono, "Interface-trap generation at ultrathin $SiO_2$ (4-6 nm)-Si interfaces during negative-bias temperature aging," J. Appl. Phys., vol. 77, pp. 1137-1148, 1995.
    • (1995) J. Appl. Phys. , vol.77 , pp. 1137-1148
    • Ogawa, S.1    Shimaya, M.2    Shiono, N.3
  • 18
    • 26444619087 scopus 로고    scopus 로고
    • "A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFETs"
    • S. Mahapatra, P. B. Kumar, and M. A. Alam, "A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFETs," in IEDM Tech. Dig., 2003, pp. 196-202.
    • (2003) IEDM Tech. Dig. , pp. 196-202
    • Mahapatra, S.1    Kumar, P.B.2    Alam, M.A.3
  • 19
    • 0036932324 scopus 로고    scopus 로고
    • "A predictive reliability model for pMOS bias temperature degradation"
    • S. Mahapatra and M. A. Alam, "A predictive reliability model for pMOS bias temperature degradation," in IEDM Tech. Dig., 2002, pp. 505-509.
    • (2002) IEDM Tech. Dig. , pp. 505-509
    • Mahapatra, S.1    Alam, M.A.2
  • 22
    • 0842266651 scopus 로고    scopus 로고
    • "A critical examination of the mechanics of dynamic NBTI for p-MOSFETs"
    • M. A. Alam, "A critical examination of the mechanics of dynamic NBTI for p-MOSFETs," in IEDM Tech. Dig., 2003, pp. 345-348.
    • (2003) IEDM Tech. Dig. , pp. 345-348
    • Alam, M.A.1
  • 24
    • 0842309776 scopus 로고    scopus 로고
    • "Universal recovery behavior of negative bias temperature instability"
    • S. Rangan, N. Mielke, and E. Yeh, "Universal recovery behavior of negative bias temperature instability," in IEDM Tech. Dig., 2003, pp. 341-344.
    • (2003) IEDM Tech. Dig. , pp. 341-344
    • Rangan, S.1    Mielke, N.2    Yeh, E.3
  • 25
    • 10044231431 scopus 로고    scopus 로고
    • "Effects of inhomogeneous negative bias temperature stress on p-channel MOSFET's of analog and RF circuits"
    • C. Schlunder, R. Brederlow, B. Ankele, W. Gustin, K. Goser, and R. Thewes, "Effects of inhomogeneous negative bias temperature stress on p-channel MOSFET's of analog and RF circuits," Microelectron. Reliab., vol. 45, pp. 39-46, 2005.
    • (2005) Microelectron. Reliab. , vol.45 , pp. 39-46
    • Schlunder, C.1    Brederlow, R.2    Ankele, B.3    Gustin, W.4    Goser, K.5    Thewes, R.6
  • 27
    • 0033733540 scopus 로고    scopus 로고
    • "A Field acceleration for oxide breakdown-can an accurate anode hole injection model resolve the E versus 1/E controversy?"
    • M. Alam, J. Bude, and J. Ghetti, "A Field acceleration for oxide breakdown-can an accurate anode hole injection model resolve the E versus 1/E controversy?," in Proc Int Reliability Phys Symp, 2000, pp. 21-26.
    • (2000) Proc Int Reliability Phys Symp , pp. 21-26
    • Alam, M.1    Bude, J.2    Ghetti, J.3
  • 29
    • 0025435018 scopus 로고
    • "Understanding wide-band MOS transistors"
    • May
    • J. M. Steininger, "Understanding wide-band MOS transistors," IEEE Circuits Devices, vol. 6, no. 3, pp. 26-31, May 1990.
    • (1990) IEEE Circuits Devices , vol.6 , Issue.3 , pp. 26-31
    • Steininger, J.M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.