Substrate bias effect linked to parasitic series resistance in multiple-gate SOI MOSFETs

IEEE Electron Device Letters

Volumn 28, Issue 9, 2007, Pages 834-836

  Rudenko, Tamara ^a   Kilchytska, Valeria ^b   Collaert, Nadine ^c   Jurczak, Malgorzata ^c   Nazarov, Alexey ^a   Flandre, Denis ^b  

^a INSTITUTE OF SEMICONDUCTOR PHYSICS   (Ukraine)

^b UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^c IMEC   (Belgium)

Author keywords

Fin field effect transistors (FinFETs); Multiple gate field effect transistors (MuGFETs); Omega gate field effect transistors; Series resistance; Short channel effect; Silicon oninsulator (SOI); Substrate bias effect

Indexed keywords

FIN FIELD-EFFECT TRANSISTORS (FINFETS); MULTIPLE-GATE FIELD-EFFECT TRANSISTORS (MUGFETS); OMEGA-GATE FIELD-EFFECT TRANSISTORS; SERIES RESISTANCE; SHORT-CHANNEL EFFECT; SILICON-ONINSULATOR (SOI); SUBSTRATE BIAS EFFECT;

DRAIN CURRENT; FINS (HEAT EXCHANGE); MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SUBSTRATES; TIME SERIES;

FIELD EFFECT TRANSISTORS;

EID: 59949101840     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.903955     Document Type: Article

References (17)

1. J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd ed. Boston, MA: Kluwer, 2004.
2. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
3. J.-T. Park and J.-P. Colinge, "Multi-gate SOI MOSFETs: Device design guidelines," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2222-2229, Dec. 2002.
4. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., Dec. 2002, pp. 251-254.
5. L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, "Gate length scaling and threshold voltage control of double-gate MOSFETs," in IEDM Tech. Dig., Dec. 2000, pp. 719-722.
6. F. Daugé, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jomaah, and B.-Y. Nguyen, "Coupling effects and channel separation in FinFETs," Solid State Electron., vol. 48, no. 4, pp. 535-542, Apr. 2004.
7. J. Pretet, S. Monfray, S. Cristoloveanu, and T. Scotnicki, "Silicon-on-nothing MOSFETs: Performance, short-channel effects, and backgate coupling," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 240-245, Feb. 2004.
8. R. Ritzenthaler, S. Cristoloveanu, O. Faynot, C. Jahan, A. Kuriyama, L. Brevard, and S. Deleonibus, "Lateral coupling and immunity to substrate effect in ΩFET devices," Solid State Electron., vol. 50, no. 4, pp. 558-565, Apr. 2006.
9. S. Cristoloveanu, "Review of radiation effects in single- and multiplegate SOI MOSFETs," in Science and Technology of Semiconductor-on-Insulator Structures and Devices Operating in a Harsh Environment, vol. 185. Boston, MA: Kluwer, 2005, pp. 197-214.
10. A. Dixit, A. Kotttantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. de Meyer, "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1132-1140, Jun. 2005.
11. K. Henson, N. Collaert, M. Demand, M. Goodwin, S. Brus, R. Rooyackers, A. van Ammel, B. Degroote, M. Ercken, C. Baerts, K. G. Anil, A. Dixit, S. Beckx, T. Schram, W. Deweerd, W. Boullart, M. Schaekers, S. De Gendt, K. De Meyer, Y. Yim, J. C. Hooker, M. Jurczak, and S. Biesemans, "NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics," in Proc. VLSI-TSA-TECH, Apr. 2005, pp. 136-137.
12. K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, "Improved split C-V method for effective mobility extraction in sub-0.1-μm Si MOSFETs," IEEE Electron Device Lett., vol. 25, no. 8, pp. 583-585, Aug. 2004.
13. T. Ouisse, S. Cristoloveanu, and G. Borel, "Influence of series resistance and interface coupling on the transconductance of fully-depleted siliconon-insulator MOSFETs," Solid State Electron. vol. 35, no. 2, pp. 141-149, Feb. 1992.
14. A. S. Nicolett, J. A. Martino, E. Simoen, and C. Claes, "Back gate voltage influence on the LDD SOI nMOSFETs: Series resistance extraction from 150 to 300 K," in NATO Science Series, vol. 73. Boston, MA: Kluwer, 2000, pp. 187-193.
15. A. Vandooren, S. Cristoloveanu, M. Mojarradi, and E. Kolawa, "Backgate and series resistance effects in LDMOSFETs on SOI," IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2410-2416, Sep. 2001.
16. J. Kedzierski, M. Ieong, E. Nowak, S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, and H.-S. P.Wong, "Extension and source/drain design for high-performance FinFET devices," IEEE Trans. Electron Devices vol. 50, no. 4, pp. 952-957, Apr. 2003.
17. D. Lederer, V. Kilchytska, T. Rudenko, N. Collaert, D. Flandre, A. Dixit, K. De Meyer, and J.-P. Raskin, "FiNFET analogue characterization from DC to 110 GHz," Solid State Electron., vol. 49, no. 9, pp. 1488-1496, Sep. 2005.