Eliminating false positives in crosstalk noise analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 9, 2005, Pages 1406-1419

  Ran, Yajun ^a,b   Kondratyev, Alex ^a,c   Tseng, Kenneth H ^c   Watanabe, Yosinori ^a,c   Marek Sadowska, Malgorzata ^a,b  

^a IEEE   (United States)

^b Santa Barbara   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Crosstalk; Noise; Satisfiability (SAT); Timed Boolean logic

Indexed keywords

ACCURATE ANALYSIS; NOISE; SATISFIABILITY (SAT); TIMED-BOOLEAN LOGIC;

BOOLEAN ALGEBRA; CROSSTALK; DELAY CIRCUITS; FLIP FLOP CIRCUITS; FORMAL LOGIC; PROBLEM SOLVING; SIGNAL PROCESSING;

ACOUSTIC NOISE;

EID: 27644510792     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.850829     Document Type: Article

References (15)

1. Celtic User Manual, Cadence Design Systems Inc., San Jose, CA, 2002.
2. Prime Time User Manual, Synopsys, Inc., Mountain View, CA, 2002.
3. R. Levy, D. Blaauw, G. Braca, A. Dasgupta, A. Grinshpon, C. Oh, B. Orshav, S. Sirichotiyakul, V. Zolotov, and T. Xiao, "Clarinet: A noise analysis tool for deep submicron design," in Proc. Design Automation Conf., Los Angeles, CA, 2000, pp. 233-238.
4. T. Xiao and M. Marek-Sadowska, "Worst delay estimation in crosstalk aware static timing analysis," in Proc. Int. Conf. on Computer Design, Austin, TX, 2000, pp. 115-120.
5. R. Arunachalam, K. Rajagopal, and L. Pileggi, "TACO: Timing analysis with coupling," in Proc. Design Automation Conf., Los Angeles, CA, 2000, pp. 266-269.
6. T. Xiao and M. Marek-Sadowska, "Functional correlation analysis in crosstalk induced critical paths identification," in Proc. Design Automation Conf., Las Vegas, NV, 2001, pp. 653-656.
7. D. Kirkpatrick and A. Sangiovanni-Vincentelli, "Digital sensitivity: Predicting signal interaction using functional analysis," in Proc. Int. Conf. on Computer-Aided Design, Austin, TX, 1996, pp. 536-541.
8. R. Arunachalam, R. D. Blanton, and L. T. Pileggi, "False coupling interactions in static timing analysis," in Proc. Design Automation Conf., Las Vegas, NV, 2001, pp. 726-731.
9. A. Glebov, S. Garrilov, D. Blaauw, S. Sirichotiyakul, C. Oh, and V. Zolotov, "False-noise analysis using logic implications," in Proc. Int. Conf. on Computer-Aided Design, Austin, TX, 2001, pp. 515-521.
10. P. Chen and K. Keutzer, "Towards true crosstalk noise analysis," in Proc. Int. Conf. on Computer-Aided Design, Austin, TX, 1999, pp. 132-137.
11. H. Zhou, "Timing analysis with crosstalk is a fixpoint on a complete lattice," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 9, pp. 1261-1269, Sep. 2003.
12. W. Lam and R. Brayton, Timed Boolean Functions: Exact Algebraic Timing Analysis. Boston, MA: Kluwer, 1994.
13. M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design. New York: IEEE Press, 1994.
14. S. Devadas and K. Keutzer, "Synthesis of robust delay-fault testable circuits: Theory," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 11, no. 1, pp. 87-101, Jan. 1992.
15. M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an efficient SAT solver," in Proc. Design Automation Conf, Las Vegas. NV, 2001, pp. 530-535.