Macro-model for post-breakdown 90NM and 130NM transistors and ITS applications in predicting chip-level function failure after ESD-CDM events

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2007, Pages 78-85

  Chen, Tze Wee ^a   Ito, Choshu ^b   Loh, William ^b   Wang, Wei ^a   Mitra, Subhasish ^a   Dutton, Robert W ^a  

^a STANFORD UNIVERSITY   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

Chip level function failure prediction; ESD CDM; Inductive coupling; Post breakdown transistor macro model

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BREAKDOWN; FAILURE ANALYSIS; MATHEMATICAL MODELS;

CHIP-LEVEL FUNCTION FAILURE PREDICTION; INDUCTIVE COUPLING; POST-BREAKDOWN TRANSISTOR MACRO-MODEL;

TRANSISTORS;

EID: 34548811999     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2007.369872     Document Type: Conference Paper

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