Design and measurement of a CT Δ ADC with switched-capacitor switched-resistor feedback

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 2, 2009, Pages 473-483

  Anderson, Martin ^a   Sundstrom, Lars ^b  

^a LUND UNIVERSITY   (Sweden)

^b ERICSSON RESEARCH   (Sweden)

Author keywords

A D conversion; Clock jitter; Delta sigma modulation

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CAPACITANCE; CAPACITORS; CLOCKS; DIELECTRIC DEVICES; DIGITAL INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; ELECTRIC INSTRUMENT TRANSFORMERS; HYBRID COMPUTERS; JITTER; MODULATION; MODULATORS; MULTICARRIER MODULATION; RESISTORS; SENSITIVITY ANALYSIS; TIMING JITTER;

A/D CONVERSION; ANALOG-TO-DIGITAL CONVERTERS; CLOCK JITTER; CLOCK PHASE; CONTINUOUS-TIME; DELTA SIGMAS; DIGITAL-TO-ANALOG CONVERTERS; LOW PASS; MINIMAL POWER; PEAK CURRENTS; PULSE WIDTHS; RETURN TO ZEROS; RF-CMOS; SECOND ORDERS; SERIES RESISTORS; SLEW RATES; SWITCHED CAPACITORS; SWITCHED CURRENTS; THEORETICAL INVESTIGATIONS; WIDE BANDS;

DELTA SIGMA MODULATION;

EID: 59349110804     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2010978     Document Type: Article

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