A continuous-time sigma-delta modulator with reduced jitter sensitivity

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 287-290

  Ortmanns, Maurits ^a   Manoli, Yiannos ^a   Gerfers, Friedel ^b  

^a UNIVERSITY OF FREIBURG   (Germany)

^b SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BIT RESOLUTION; CONTINUOUS-TIME SIGMA-DELTA MODULATORS; D/A CONVERTERS; DISCRETE TIME; LOW POWER; SWITCHED CAPACITOR;

CONTINUOUS TIME SYSTEMS; JITTER;

MODULATORS;

EID: 84893789916     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. F. Gerfers, M. Ortmanns, Y. Manoli, "A 12 bit power efficient continuous-time η&deta â § modulator with 250μW power consumption", Proc. ESSCirC, 2001, pp. 536-539.
2. J.A. Cherry, W.M. Snelgrove, "Excess Loop Delay in Continuous-Time Delta-Sigma Modulators", IEEE Trans. on Cir. And Sys.-II, 1999, Vol.46, pp. 376-389.
3. J.A. Cherry, W.M. Snelgrove, "Clock Jitter and Quantizer Metastability in Continuous-Time η&deta; Modulators," IEEE Trans. on Cir. And Sys.-II, 1999, vol. 46, pp. 661-676.
4. H. Tao, L. Toth, J.M. Khoury, "Analysis of timing jitter in bandpass sigma-delta modulators," IEEE Trans. on Cir. And Sys.-II, 1999, vol. 46, pp. 991-1001.
5. M. Ortmanns, F. Gerfers, and Y. Manoli, "Jitter insensitive Feedback DAC for Continuous-Time η&deta; § Modulators", Proc. ICECS, 2001, pp. 1049-1053.