-
1
-
-
0027297425
-
Near shannon limit error-correcting coding and decoding: Turbo-codes
-
C. Berrou, A. Glavieux and P. Thitimajshima, "Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes," IEEE Int. Conf. on Communications, vol. 2, pp. 1064-1070, 1993.
-
(1993)
IEEE Int. Conf. on Communications
, vol.2
, pp. 1064-1070
-
-
Berrou, C.1
Glavieux, A.2
Thitimajshima, P.3
-
2
-
-
0019612636
-
Sliding block decoding of convolutional codes
-
Sep.
-
K.-H. Tzou and J. G. Dunham, "Sliding Block Decoding of Convolutional Codes," IEEE Trans. Commun., Vol. 29, No. 9, pp. 1401-1403, Sep. 1981.
-
(1981)
IEEE Trans. Commun.
, vol.29
, Issue.9
, pp. 1401-1403
-
-
Tzou, K.-H.1
Dunham, J.G.2
-
3
-
-
0036053036
-
A 80 Mb/s low-power scalable turbo codec core
-
A. Giulietti et al, "A 80 Mb/s low-power scalable turbo codec core," Proc. CICC, pp. 389-392, 2002.
-
(2002)
Proc. CICC
, pp. 389-392
-
-
Giulietti, A.1
-
4
-
-
84903327629
-
A scalable system architecture for high-throughput turbo-decoders
-
Feb.
-
M. J. Thul et al, "A scalable system architecture for high-throughput turbo-decoders," Kluwer Journal VLSI, Feb. 2003.
-
(2003)
Kluwer Journal VLSI
-
-
Thul, M.J.1
-
5
-
-
0036625313
-
Architectural strategies for low-power VLSI turbo decoders
-
June
-
G. Masera, M. Mazza, G. Piccinini, F. Viglione and M. Zamboni, "Architectural strategies for low-power VLSI turbo decoders," IEEE Trans. on VLSI Systems, vol. 10, no. 3, pp. 279-285, June 2002.
-
(2002)
IEEE Trans. on VLSI Systems
, vol.10
, Issue.3
, pp. 279-285
-
-
Masera, G.1
Mazza, M.2
Piccinini, G.3
Viglione, F.4
Zamboni, M.5
-
6
-
-
0003819663
-
-
San Mateo, CA, USA, Morgan Kaufmann Publishers
-
F. T. Leighton. "Introduction to parallel algorithms and architectures: arrays, trees and hypercubes," San Mateo, CA, USA, Morgan Kaufmann Publishers, 1992.
-
(1992)
Introduction to Parallel Algorithms and Architectures: Arrays, Trees and Hypercubes
-
-
Leighton, F.T.1
-
7
-
-
0036641818
-
Implementation of scalable power and area efficient high-throughput Viterbi decoders
-
July
-
T. Gemmeke, M. Gansen and T. G. Noll, "Implementation of scalable power and area efficient high-throughput Viterbi decoders," IEEE J. of Solid-State Circuits, vol. 37, no. 7, pp. 941-948, July 2002.
-
(2002)
IEEE J. of Solid-state Circuits
, vol.37
, Issue.7
, pp. 941-948
-
-
Gemmeke, T.1
Gansen, M.2
Noll, T.G.3
-
8
-
-
0037168148
-
Design of dividable interleaver for parallel decoding in turbo codes
-
October
-
J. Kwak and K. Lee, "Design of dividable interleaver for parallel decoding in turbo codes," Electr. Letters, vol. 38, no. 22, pp 1362-1364, October 2002.
-
(2002)
Electr. Letters
, vol.38
, Issue.22
, pp. 1362-1364
-
-
Kwak, J.1
Lee, K.2
-
9
-
-
0000035405
-
Optimal and sub-optimal maximum a posteriori algorithms for turbo decoding
-
P. Robertson, P. Hoeher and E. Villebrun, "Optimal and sub-optimal maximum a posteriori algorithms for turbo decoding," Europ. Trans. on Telecomm., vol. 8, no. 2, pp. 119-125, 1997.
-
(1997)
Europ. Trans. on Telecomm.
, vol.8
, Issue.2
, pp. 119-125
-
-
Robertson, P.1
Hoeher, P.2
Villebrun, E.3
-
11
-
-
3042739407
-
Design otimization of low-power high-performance DSP building blocks
-
July
-
T. Gemmeke, M. Gansen, H. Stockmanns and T.G. Noll, "Design otimization of low-power high-performance DSP building blocks," IEEE J. of Sol. State. Circ., vol. 39, no. 7, pp.1131-1139, July 2004.
-
(2004)
IEEE J. of Sol. State. Circ.
, vol.39
, Issue.7
, pp. 1131-1139
-
-
Gemmeke, T.1
Gansen, M.2
Stockmanns, H.3
Noll, T.G.4
-
12
-
-
17144472503
-
Implementation of a parallel turbo decoder with dividable interleaver
-
May
-
J. Kwak, S. M. Park, S. S. Yoon and K. Lee, "Implementation of a parallel turbo decoder with dividable interleaver," Proc. Int. Symp. on Circuits and Systems, vol. 2, pp. 65-68, May 2003.
-
(2003)
Proc. Int. Symp. on Circuits and Systems
, vol.2
, pp. 65-68
-
-
Kwak, J.1
Park, S.M.2
Yoon, S.S.3
Lee, K.4
|