A reconfigurable application specific instruction set processor for viterbi and log-MAP decoding

2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS

Volumn , Issue , 2006, Pages 142-147

  Vogt, Timo ^a,b   Wehn, Norbert ^a,b  

^a IEEE

^b Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHANNEL CODING; CODES (STANDARDS); CODES (SYMBOLS); COMMUNICATION; CONVOLUTIONAL CODES; DATA STORAGE EQUIPMENT; MAPS; MOTION ESTIMATION; NETWORK ARCHITECTURE; OIL WELL LOGGING; PIPELINES; PROGRAMMING THEORY; SIGNAL PROCESSING; STANDARDS; TELECOMMUNICATION; TELECOMMUNICATION SYSTEMS; THROUGHPUT; TURBO CODES;

APPLICATION DOMAINS; APPLICATION-SPECIFIC INSTRUCTION-SET PROCESSOR (ASISP); DUOBINARY; FUTURE SYSTEMS; HIGH PERFORMANCE; LOG MAP; MAXIMUM THROUGH PUT; MOBILE AND WIRELESS COMMUNICATIONS; RE-CONFIGURABLE; SIGNAL PROCESSING SYSTEMS; SYNTHESIS (OF CHIRAL IONIC LIQUIDS); VITERBI; WIRELESS (WIFI) COMMUNICATION; WIRELESS COMMUNICATION STANDARDS;

DECODING;

EID: 43549095615     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2006.352570     Document Type: Conference Paper

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