BENoC: A bus-enhanced network on-chip for a power efficient CMP

IEEE Computer Architecture Letters

Volumn 7, Issue 2, 2008, Pages 61-64

  Walter, Isask'Har ^a   Cidon, Israel ^a   Kolodny, Avinoam ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Interconnection architectures; Network on Chip support for CMP; On chip interconnection networks

Indexed keywords

BIOLOGICAL MATERIALS; BUSES; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; METROPOLITAN AREA NETWORKS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; TELECOMMUNICATION NETWORKS;

BROADCAST OPERATIONS; BROADCAST TRANSMISSIONS; CACHE ACCESSES; CENTRALIZED CONTROLS; HIGH THROUGHPUTS; INFRA STRUCTURES; INTERCONNECTION ARCHITECTURES; LOW LATENCIES; MULTIPROCESSOR SYSTEMS; NETWORK ON-CHIP SUPPORT FOR CMP; NOC ARCHITECTURES; NON UNIFORMS; ON-CHIP INTERCONNECTION NETWORKS; POINT DATUMS; POTENTIAL BENEFITS; POWER SAVINGS; PROPOSED ARCHITECTURES; SENSITIVE SIGNALS; SHARED BUSES; SYSTEM MODULARITY;

BROADCASTING;

EID: 58149127797     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2008.11     Document Type: Article

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