Multilevel k-way hypergraph partitioning

VLSI Design

Volumn 11, Issue 3, 2000, Pages 285-300

  Karypis, George ^a   Kumar, Vipin ^a,b  

^a University of Minnesota   (United States)

^b IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK ANALYSIS; HEURISTIC METHODS; OPTIMIZATION;

CIRCUIT PARTITIONING; HYPERGRAPH PARTITIONING;

VLSI CIRCUITS;

EID: 0034538133     PISSN: 1065514X     EISSN: None     Source Type: None    
DOI: 10.1155/2000/19436     Document Type: Article

References (26)

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