Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO

Microelectronics Journal

Volumn 40, Issue 1, 2009, Pages 95-103

  Kougianos, Elias ^a   Mohanty, Saraju P ^a  

^a UNIVERSITY OF NORTH TEXAS   (United States)

Author keywords

Design of experiments; Gate oxide leakage; Gate oxide tunneling; Nanoscale CMOS; Voltage controlled oscillator

Indexed keywords

ANALOG CIRCUITS; ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DENSITY (OPTICAL); DESIGN OF EXPERIMENTS; DIFFRACTIVE OPTICAL ELEMENTS; DIGITAL TO ANALOG CONVERSION; ELECTRON TUNNELING; EXPERIMENTS; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; NETWORKS (CIRCUITS); OPTICAL PROPERTIES; OPTIMIZATION; SPECIFICATIONS; TUNNELING (EXCAVATION); VARIABLE FREQUENCY OSCILLATORS; VOLTAGE DIVIDERS;

ACCURATE MODELING; ACTIVE AREAS; CASE STUDIES; CENTER FREQUENCIES; CMOS TECHNOLOGIES; CMOS VCO; DESIGN OPTIMIZATIONS; DESIGN PARAMETERS; DESIGN SPECIFICATIONS; DEVICE PERFORMANCES; DIGITAL BLOCKS; DIGITAL SIMULATIONS; FREQUENCY DIVIDERS; FUNCTIONAL SPECIFICATIONS; GATE TUNNELING CURRENTS; GATE-OXIDE LEAKAGE; GATE-OXIDE TUNNELING; MINIMIZATION OF POWERS; MIXED SIGNALS; MIXED-SIGNAL CIRCUITS; NANOMETER REGIMES; NANOMETER SCALES; NANOSCALE CMOS; OPTIMIZATION GOALS; OVERALL POWERS; OXIDE THICKNESSES; OXIDE TUNNELING CURRENTS; PERFORMANCE CHARACTERISTICS; PERFORMANCE ENHANCEMENTS; STANDARD DESIGNS; TECHNOLOGY SCALING; TRANSISTOR SIZES; TUNNELING CAPACITANCES; VOLTAGE CONTROLLED OSCILLATOR;

DESIGN;

EID: 57849117380     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2008.08.017     Document Type: Article

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