Analog circuit performance issues with aggressively scaled gate oxide CMOS technologies

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2006, Issue , 2006, Pages 45-50

  Narasimhulu, K ^a   Ramgopal Rao, V ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); DIELECTRIC MATERIALS; GATES (TRANSISTOR); LEAKAGE CURRENTS; NETWORKS (CIRCUITS); OXIDES;

AMPLIFIER CIRCUITS; CURRENT MIRROR CIRCUITS; GATE LEAKAGE; GATE OXIDES;

CMOS INTEGRATED CIRCUITS;

EID: 33748527760     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2006.84     Document Type: Conference Paper

References (7)

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2. R. van Langevelde et. al., "Gate current: modelling, ΔL extraction and impact of RF performance", Proc. of IEDM pp.289-93, 2001
3. Anne-Johan Annema et. al., "Analog Circuits in Ultra-Deep-Sub micron CMOS", IEEE Journal of Solid-State Circuits, vol.40, pp. 132-43, Jan. 2005.
4. B. Razavi, "Design of analogue Integrated circuits", McGraw Hill Publishing Company 2001.
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