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Volumn , Issue , 2008, Pages 83-86

Dual material gate oxide stack symmetric double gate MOSFET: Improving short channel effects of nanoscale double gate MOSFET

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; DRAIN CURRENT; SILICON COMPOUNDS; THRESHOLD VOLTAGE;

EID: 57849084054     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BEC.2008.4657483     Document Type: Conference Paper
Times cited : (32)

References (11)
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  • 2
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    • M. J. Kumar and A. A. Orouji, "Two-Dimensional Analytical Threshold Voltage Model of Nanoscale Fully Depleted SOI MOSFET with Electrically Induced Source/Drain Extensions," IEEE Trans. Electron Devices, vol. 52, no.7, pp. 1568-1575, 2005.
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    • Kumar, M.J.1    Orouji, A.A.2
  • 3
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    • Shielded Channel-Double Gate (SC-DG) MOSFET: A Novel Device for Reliable Nanoscale CMOS Applications
    • A. A. Orouji and M. J. Kumar, "Shielded Channel-Double Gate (SC-DG) MOSFET: A Novel Device for Reliable Nanoscale CMOS Applications," IEEE Trans. Device and Materials Reliability, vol. 5, no. 3, pp. 509-514, 2005.
    • (2005) IEEE Trans. Device and Materials Reliability , vol.5 , Issue.3 , pp. 509-514
    • Orouji, A.A.1    Kumar, M.J.2
  • 4
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    • (1994) IEEE Electron Device Lett , vol.15 , Issue.10 , pp. 386-388
    • Tanaka, T.1    Suzuki, K.2    Horie, H.3    Sugii, T.4
  • 6
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    • Simulation-based assessment of 50 nm double-gate SOI CMOS performance
    • Oct
    • J. G. Fossum and Y. Chong, "Simulation-based assessment of 50 nm double-gate SOI CMOS performance," In Proc. IEEE Int. SOI Conf., pp.107-108, Oct. 1998,
    • (1998) In Proc. IEEE Int. SOI Conf , pp. 107-108
    • Fossum, J.G.1    Chong, Y.2
  • 7
    • 0032284102 scopus 로고    scopus 로고
    • Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation
    • Dec
    • H. P. Wong, D. J. Frank, and P. M. Solomon, "Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation," Int. Electron Devices Meeting (IEDM) Tech. Dig., pp. 407-410, Dec. 1998.
    • (1998) Int. Electron Devices Meeting (IEDM) Tech. Dig , pp. 407-410
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  • 8
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    • 1.5 nm direct tunneling gate oxide si MOSFETs
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  • 9
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.