-
1
-
-
2342583496
-
Controlling short-channel effects in deep submicron SOI MOSFETS for improved reliability: A review
-
March
-
A. Chaudry and M. J. Kumar, "Controlling short-channel effects in deep submicron SOI MOSFETS for improved reliability: a review", IEEE Trans on Device and Materials Reliability, vol. 4, no. 1, pp. 99-109 March 2004.
-
(2004)
IEEE Trans on Device and Materials Reliability
, vol.4
, Issue.1
, pp. 99-109
-
-
Chaudry, A.1
Kumar, M.J.2
-
2
-
-
23944447436
-
Two-Dimensional Analytical Threshold Voltage Model of Nanoscale Fully Depleted SOI MOSFET with Electrically Induced Source/Drain Extensions
-
M. J. Kumar and A. A. Orouji, "Two-Dimensional Analytical Threshold Voltage Model of Nanoscale Fully Depleted SOI MOSFET with Electrically Induced Source/Drain Extensions," IEEE Trans. Electron Devices, vol. 52, no.7, pp. 1568-1575, 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.7
, pp. 1568-1575
-
-
Kumar, M.J.1
Orouji, A.A.2
-
3
-
-
29344473782
-
Shielded Channel-Double Gate (SC-DG) MOSFET: A Novel Device for Reliable Nanoscale CMOS Applications
-
A. A. Orouji and M. J. Kumar, "Shielded Channel-Double Gate (SC-DG) MOSFET: A Novel Device for Reliable Nanoscale CMOS Applications," IEEE Trans. Device and Materials Reliability, vol. 5, no. 3, pp. 509-514, 2005.
-
(2005)
IEEE Trans. Device and Materials Reliability
, vol.5
, Issue.3
, pp. 509-514
-
-
Orouji, A.A.1
Kumar, M.J.2
-
5
-
-
0028532218
-
Ultrafast operation of Vth-adjusted p+ - n+ double-gate SOI MOSFETs
-
Oct
-
T. Tanaka, K. Suzuki, H. Horie, and T. Sugii, "Ultrafast operation of Vth-adjusted p+ - n+ double-gate SOI MOSFETs," IEEE Electron Device Lett., vol. 15, no. 10, pp. 386-388, Oct. 1994.
-
(1994)
IEEE Electron Device Lett
, vol.15
, Issue.10
, pp. 386-388
-
-
Tanaka, T.1
Suzuki, K.2
Horie, H.3
Sugii, T.4
-
6
-
-
0032306225
-
Simulation-based assessment of 50 nm double-gate SOI CMOS performance
-
Oct
-
J. G. Fossum and Y. Chong, "Simulation-based assessment of 50 nm double-gate SOI CMOS performance," In Proc. IEEE Int. SOI Conf., pp.107-108, Oct. 1998,
-
(1998)
In Proc. IEEE Int. SOI Conf
, pp. 107-108
-
-
Fossum, J.G.1
Chong, Y.2
-
7
-
-
0032284102
-
Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation
-
Dec
-
H. P. Wong, D. J. Frank, and P. M. Solomon, "Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation," Int. Electron Devices Meeting (IEDM) Tech. Dig., pp. 407-410, Dec. 1998.
-
(1998)
Int. Electron Devices Meeting (IEDM) Tech. Dig
, pp. 407-410
-
-
Wong, H.P.1
Frank, D.J.2
Solomon, P.M.3
-
8
-
-
0030212001
-
1.5 nm direct tunneling gate oxide si MOSFETs
-
H. S. Momose, M. Ono, and T. Yositomi, "1.5 nm direct tunneling gate oxide si MOSFETs", IEEE Trans. on Electron Devices, vol. 43, no. 8, pp. 1233-1242, 1996.
-
(1996)
IEEE Trans. on Electron Devices
, vol.43
, Issue.8
, pp. 1233-1242
-
-
Momose, H.S.1
Ono, M.2
Yositomi, T.3
-
9
-
-
0032072440
-
Fringing induced barrier lowering in sub-100 nm MOSFETs with high-k gate dielectrics
-
G. C. F. Yeap, S. Krishnan, and M. R. Lin, "Fringing induced barrier lowering in sub-100 nm MOSFETs with high-k gate dielectrics", IEEE Electron Device Lett. vol. 34, no. 11, pp. 1150-1152, 1998.
-
(1998)
IEEE Electron Device Lett
, vol.34
, Issue.11
, pp. 1150-1152
-
-
Yeap, G.C.F.1
Krishnan, S.2
Lin, M.R.3
-
10
-
-
57849108215
-
-
SILVACO International 2000, ATLAS: 2-D Device Simulation Software.
-
SILVACO International 2000, ATLAS: 2-D Device Simulation Software.
-
-
-
-
11
-
-
0032670723
-
Dual material gate (DMG) field effect transistor
-
May
-
W. Long, H. Ou, J.-M. Kuo, and K. K. Chin, "Dual material gate (DMG) field effect transistor," IEEE Trans. on Electron Devices, vol. 46, no. 5, pp. 865-870, May 1999.
-
(1999)
IEEE Trans. on Electron Devices
, vol.46
, Issue.5
, pp. 865-870
-
-
Long, W.1
Ou, H.2
Kuo, J.-M.3
Chin, K.K.4
|