Integrating clock gating and power gating for combined dynamic and leakage power optimization in digital CMOS circuits

Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008

Volumn , Issue , 2008, Pages 298-306

  Macii, E ^a   Bolzani, L ^a   Calimera, A ^a   Macii, A ^a   Poncino, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Digital CMOS circuits; Dynamic power optimization; Leakage power optimization

Indexed keywords

ARCHITECTURAL DESIGN; CLOCKS; DIGITAL CIRCUITS; INTEGRATION; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; OPTIMIZATION; SYSTEMS ANALYSIS;

CAD TOOLS; CLOCK GATING; CMOS CIRCUITS; CONTROL LOGICS; DIGITAL CMOS CIRCUITS; DYNAMIC POWER OPTIMIZATION; JOINT APPLICATIONS; LEAKAGE POWER OPTIMIZATION; LEAKAGE POWERS; POWER GATING; POWER SAVINGS;

COMPUTER AIDED DESIGN;

EID: 57649165792     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2008.90     Document Type: Conference Paper

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