Optimal MTCMOS reactivation under power supply noise and performance constraints

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 973-978

  Calimera, Andrea ^a   Benini, Luca ^b   Macii, Enrico ^a  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; BENCHMARK CIRCUITS; CIRCUIT BLOCKS; DISCHARGE CURRENTS; GROUND BOUNCE; HSPICE SIMULATIONS; IR DROPS; NANOMETER CIRCUITS; ON CURRENTS; OPTIMAL SIZING; PERFORMANCE CONSTRAINTS; POWER MODES; POWER-SUPPLY FLUCTUATIONS; POWER-SUPPLY NOISE; SEQUENTIAL ACTIVATION; SLEEP TRANSISTORS; STAND-BY LEAKAGE; WAKE-UP LATENCY;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER TRANSMISSION NETWORKS; ELECTRIC POWER UTILIZATION; EPITAXIAL GROWTH; INDUSTRIAL ENGINEERING; PARALLEL ALGORITHMS; SEQUENTIAL SWITCHING; SOLUTIONS; TESTING; TRANSISTORS; VLSI CIRCUITS;

NETWORKS (CIRCUITS);

EID: 49749116753     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484807     Document Type: Conference Paper

References (10)

1. C. Long, L. He, "Distributed Sleep Transistor Network for Power Reduction," IEEE TVLSI, Vol. 12, No. 9, pp. 937-946, Sep. 2004.
2. P. Babighian, L. Benini, A. Macii, E. Macii, "Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion," ISLPED-04, pp. 138-143, Aug. 2004.
3. D. S. Chiou, et al., "Timing Driven Power Gating," DAC-06, pp. 121-124, Jul. 2006.
4. A. Sathanur, A. Pullini, L. Benini, A. Macii, E. Macii, M. Poncino, "Timing Driven Row-Based Power Gating," ISLPED-07, Aug. 2007.
5. S. Kim, S. V. Kosonocky, D. R. Knebel "Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structures," ISLPED-03 pp. 22-25, Aug. 2003.
6. D. Howard, K. Shi "Power-On Current Control In Sleep Transistor Implementations," DATE-06, pp. 1-4, Apr. 2006.
7. S. Henzler, et al., "Activation Technique for Sleep-Transistor Circuits for Reduced Power Supply Noise," ESSCIRC-06, pp. 102-105, Sep. 2006.
8. C. Chang, et al., "New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode," ISCAS-07, pp. 3740-3743, May 2007.
9. A. Abdollahi, F. Fallah, M. Pedram "A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design," IEEE TVLSI, Vol. 15, No. 1, pp. 80-89, Jan. 2007.
10. A. Sathanur, A. Calimera, L. Benini, A. Macii, E. Macii, M. Poncino, "Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing," DATE-07, pp. 1-6, Apr. 2007.