-
1
-
-
0022738392
-
A four-state EEPROM using floating-gate memory cells
-
Mar.
-
C. Bleiker and H. Melchior, "A four-state EEPROM using floating-gate memory cells," IEEE J. Solid-State Circuits, vol. SC-22, p. 460, Mar. 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.SC-22
, pp. 460
-
-
Bleiker, C.1
Melchior, H.2
-
2
-
-
0029253928
-
A multilevel-cell 32 Mb flash memory
-
M. Bauer, R. Alexis, G. Atwood, B. Baltar, A. Fazio, K. Frary, M. Hensel, M. Ishac, J. Javanifard, M. Landgraf, D. Leak, K. Loe, D. Mills, P. Ruby, R. Rozman, S. Sweha, S. Talreja, and K. Wojciechowski, "A multilevel-cell 32 Mb flash memory," in IEEE Int. Solid-State Circuits Conf. Dig., 1995, p. 132.
-
(1995)
IEEE Int. Solid-State Circuits Conf. Dig.
, pp. 132
-
-
Bauer, M.1
Alexis, R.2
Atwood, G.3
Baltar, B.4
Fazio, A.5
Frary, K.6
Hensel, M.7
Ishac, M.8
Javanifard, J.9
Landgraf, M.10
Leak, D.11
Loe, K.12
Mills, D.13
Ruby, P.14
Rozman, R.15
Sweha, S.16
Talreja, S.17
Wojciechowski, K.18
-
3
-
-
0029480949
-
Fast and accurate programming method for multilevel NAND EEPROM's
-
G. J. Hemink, T. Tanaka, T. Endoh, S. Aritome, and R. Shirota, "Fast and accurate programming method for multilevel NAND EEPROM's," in Symp. VLSI Technol. Dig. 1995, p. 129.
-
(1995)
Symp. VLSI Technol. Dig.
, pp. 129
-
-
Hemink, G.J.1
Tanaka, T.2
Endoh, T.3
Aritome, S.4
Shirota, R.5
-
4
-
-
0030288232
-
A 98-mm die size 3.3 V 64 Mb flash memory with FN-NOR type four-level cell
-
Nov.
-
M. Ohkawa, H. Sugawara, N. Sudo, M. Tsukiji, K. Nadagawa, M. Kawata, K. Oyama, T. Takeshima, and S. Ohya, "A 98-mm die size 3.3 V 64 Mb flash memory with FN-NOR type four-level cell," IEEE J. Solid-State Circuits, vol. 31, p. 1584, Nov. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 1584
-
-
Ohkawa, M.1
Sugawara, H.2
Sudo, N.3
Tsukiji, M.4
Nadagawa, K.5
Kawata, M.6
Oyama, K.7
Takeshima, T.8
Ohya, S.9
-
5
-
-
0030291637
-
2 3.3 V only 128 Mb multilevel NAND flash memory for mass storage applications
-
Nov.
-
2 3.3 V only 128 Mb multilevel NAND flash memory for mass storage applications," IEEE J. Solid-State Circuits, vol. 31, p. 1575, Nov. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 1575
-
-
Jung, T.S.1
Choi, Y.J.2
Suh, K.D.3
Suh, B.H.4
Kim, J.K.5
Lim, Y.H.6
Koh, Y.N.7
Park, J.W.8
Lee, K.J.9
Park, J.H.10
Park, K.T.11
Kim, J.R.12
Yi, J.H.13
Lim, H.K.14
-
6
-
-
0030387349
-
Multilevel flash cells and their trade-offs
-
B. Eitan, R. Kazerounian, and A. Roy, "Multilevel flash cells and their trade-offs," in IEEE IEDM Tech. Dig., 1996, p. 169.
-
(1996)
IEEE IEDM Tech. Dig.
, pp. 169
-
-
Eitan, B.1
Kazerounian, R.2
Roy, A.3
-
7
-
-
0029714969
-
Impact of cell threshold voltage distribution in the array of flash memories on scaled and multilevel flash cell design
-
K. Yoshikawa, "Impact of cell threshold voltage distribution in the array of flash memories on scaled and multilevel flash cell design," in Symp. VLSI Technol. Dig., 1996, p. 240.
-
(1996)
Symp. VLSI Technol. Dig.
, pp. 240
-
-
Yoshikawa, K.1
-
9
-
-
0029493274
-
Multilevel flash/EPROM memories: New self-convergent programming methods for low-voltage applications
-
M. Chi and A. Bergemont, "Multilevel flash/EPROM memories: New self-convergent programming methods for low-voltage applications," IEEE IEDM Tech. Dig., 1995, p. 271.
-
(1995)
IEEE IEDM Tech. Dig.
, pp. 271
-
-
Chi, M.1
Bergemont, A.2
-
10
-
-
3843137552
-
A sixteen-level scheme for multilevel flash EEPROM's
-
D. L. Kencke, R. Richart, S. Garg, and S. K. Banerjee, "A sixteen-level scheme for multilevel flash EEPROM's," in IEEE IEDM Tech. Dig., 1996, p. 937.
-
(1996)
IEEE IEDM Tech. Dig.
, pp. 937
-
-
Kencke, D.L.1
Richart, R.2
Garg, S.3
Banerjee, S.K.4
-
11
-
-
0019241670
-
Data retention in EPROM's
-
R. E. Shiner, J. M. Caywood, and B. L. Euzent, "Data retention in EPROM's," in Proc. IRPS, 1980, p. 238.
-
(1980)
Proc. IRPS
, pp. 238
-
-
Shiner, R.E.1
Caywood, J.M.2
Euzent, B.L.3
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