The quarter-state sequence (Q-sequence) to represent the floorplan and applications to layout optimization

IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

Volumn , Issue , 2000, Pages 829-832

  Sakanushi, Keishi ^a   Kajitani, Yoji ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

4 direction; Count; Floorplan; Q sequence; Topological packing

Indexed keywords

ALGORITHMS; BOUNDARY VALUE PROBLEMS; COMBINATORIAL MATHEMATICS; DECODING; ENCODING (SYMBOLS); GLOBAL OPTIMIZATION; NUMERICAL ANALYSIS; PROBLEM SOLVING; STOCHASTIC PROGRAMMING; THEOREM PROVING;

4-DIRECTION; COUNT; FLOORPLAN; Q-SEQUENCE; TOPOLOGICAL PACKING;

VLSI CIRCUITS;

EID: 0005497664     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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