A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n+-doped polysilicon

IEEE Transactions on Electron Devices

Volumn 51, Issue 10, 2004, Pages 1644-1652

  Son, Nak Jin ^a   Oh, Yongchul ^a   Kim, Wookje ^a   Jang, Se Myeong ^a   Yang, Wouns ^a   Jin, Gyoyoung ^a   Park, Donggun ^a   Kim, Kinam ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINA; AMORPHOUS SILICON; CAPACITOR STORAGE; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; HAFNIUM COMPOUNDS; ION IMPLANTATION; MOSFET DEVICES; OPTIMIZATION; POLYSILICON; RELIABILITY; SEMICONDUCTOR DOPING;

CMOSFET; DUAL POLY GATE TECHNOLOGY; GATE OXIDE RELIABILITY; LOW POWER DYNAMIC RANDOM ACCESS MEMORY; NEGATIVE WORD LINE (NWL); PLASMA NITRIDATION; RETENTION TIME; TUNGSTEN POLYCIDE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 5444233117     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.835162     Document Type: Article

References (25)

1. + polysilicon-gate MOSFETs instability with fluorine incorporation," IEEE Trans. Electron Devices, vol. 37, pp. 2312-2321, Nov. 1990.
2. +-polysilicon gate MOS," IEEE Trans. Electron Devices, vol. 48, pp. 2777-2784, Dec. 2001.
3. 14) implantation into polysilicon gate on high-performance dual-gate CMOS transistors," IEEE Electron Device Lett., vol. 18, pp. 312-314, July 1997.
4. M. Cao, P. V. Voorde, M. Cox, and W. Greene, "Boron diffusion and penetration in ultrathin oxide with poly-Si gate," IEEE Electron Device Lett., vol. 19, pp. 291-293, Aug. 1998.
5. + polysilicon gate using Si-B diffusion source," Electron. Lett., vol. 34, pp. 128-129, Jan. 1998.
6. 2 interface degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET," IEEE Electron Device Lett, vol. 15, pp. 160-162, May 1994.
7. H. Koike, Y. Unno, F. Matsuoka, and M. Kakumn, "Dual-polycide gate technology using regrowth amorphous-Si to suppress lateral dopant diffusion," IEEE Trans. Electron Devices, vol. 44, pp. 1460-1466, Sept. 1997.
8. +-polysilicon gated MOS device applications," IEEE Electron Device Lett, vol. 16, pp. 319-321, July 1995.
9. M. Tanaka, S. Saida, I. Mizushima, F. Inoue, M. Kojima, T. Tanaka, T. Nakanishi, K. Suguro, and Y. Tsunashima, "Suppression of SiN-induced boron penetration by using Si-H free silicon nitride films formed by tetrachlorosilane and ammonia," IEEE Trans. Electron Devices, vol. 49, pp. 1526-1531, Sept. 2002.
10. 2O anneal," IEEE Electron Device Lett, vol. 15, pp. 109-111, Mar. 1994.
11. 2 vertical DRAM cell," in VLSI Symp. Tech. Dig., 2002, pp. 58-59.
12. M. Togo et al., "Thermally robust dual-gate CMOS integration technologies for high-performance DRAM-embedded ASICs," in IEDM Tech. Dig., 1999, pp. 49-52.
13. N. Takenaka et al., "High density embedded DRAM technology with 0.38 μm pich in DRAM and 0.42 μm pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization," in VLSI Symp. Tech. Dig., 2000, pp. 62-63.
14. Y. Hiura, A. Azuma, K. Nakajima, Y. Akasaka, K. Miyano, H. Nitta, A. Honjo, K. Tsuchida, Y. Toyoshima, K. Suguro, and Y. Kohyama, "Intergration technology of polymetal (W/WSiN/Poly-Si) dual-gate CMOS for 1 Gbit DRAMs and beyound," in IEDM Tech. Dig., 1998, pp. 389-392.
15. J. Y. Sim, Y. G. Gang, K. N. Lim, J. Y. Choi, S. K. Kwak, K. C. Chun, J. H. Yoo, D. I. Seo, and S. I. Cho, "Charge-transferred pre-sensing and efficiently precharged negative word-line schemes for low-voltage DRAMs," in VLSI Symp. Tech. Dig., 2003, pp. 289-292.
16. H. Tanaka, M. Aoki, T. Sakata, S. Kimura, N. Sakashita, and K. Kimura, "A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme," IEEE J. Solid-State Circuits, vol. 34, pp. 1084-1090, Aug. 1999.
17. S. Eto, M. Matsumiya, M. Takita, Y. Ishii, T. Nakamura, K. Kawabata, A. Kitamoto, T. Ikeda, M. Higashiho, Y. Serizawa, K. Itabashi, O. Tsuboi, Y. Yokoyama, and M. Taguchi, "A 1-Gb SRAM with ground-level precharged bit line and nonboosted 2.1-V word line," IEEE J. Solid-State Circuits, vol. 33, pp. 1697-1702, Nov. 1998.
18. J. H. Lee, J. H. Lee, Y. S. Kim, H. S. Jung, N. I. Lee, H. K. Kang, and K. P. Suh, "Practical next generation solution for stand-alone and embedded DRAM capacitor," in VLSI Symp. Tech. Dig., 2002, pp. 114-115.
19. A. Hegedus, C. S. Olsen, N. Kuan, and J. Madok, "Clustering of plasma nitridation and post-anneal steps to improve threshold voltage repeatability," IEEE Trans. Semiconduct. Manufact., vol. 16, pp. 165-169, May 2003.
20. H. Hayashida, Y. Toyoshima, Y. Suizu, K. Mitsyhashi, H. Iwai, and K. Maeguchi, "Dopant redistribution in dual-gate W-polycide CMOS and its improvement by RTA," in VLSI Symp. Tech. Dig., 1989, pp. 29-30.
21. Z. Wang, C. G. Parker, D. W. Hodge, R. T. Croswell, N. Yang, V. Misra, and J. R. Hauser, "Effect of polysilicon gate type on the flatband voltage shift for ultrathin oxide-nitride gate stacks," IEEE Electron Device Lett., vol. 21, pp. 170-172, Apr. 2000.
22. T. Hori, "Inversion layer mobility under high normal field in nitrided-oxide MOSFETs," IEEE Trans. Electron Devices, vol. 37, pp. 2058-2069, Sept. 1990.
23. 2-implanted P-type gate MOSFET by trapping of fluorine in amorphous gate," IEEE Trans. Electron Devices, vol. 42, pp. 1503-1509, Sept. 1995.
24. x-polycide gate processes on MOSFET reliability for giga-bit scale DRAMs," in Proc. IRW, 2000, pp. 125-128.
25. T. B. Hook, E. Alder, F. Guarin, J. Lukaitis, N. Rovedo, and K. Schruefer, "The effects of fluorine on parametrics and reliability in a 0.18-μm 3.5/6.8 nm dual-gate oxide CMOS technology," IEEE Trans. Electron Devices, vol. 48, pp. 1346-1353, July 2001.