High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2000, Pages 62-63

  Takenaka, N ^a   Segawa, M ^a   Uehara, T ^a   Akamatsu, S ^a   Matsumoto, M ^a   Kurimoto, K ^a   Ueda, T ^a   Watanabe, H ^a   Matsutani, T ^a   Yoneda, K ^a   Koshio, A ^a   Kato, Y ^a   Inuishi, M ^a   Oashi, T ^a   Tsukamoto, K ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC CONTACTS; GATES (TRANSISTOR); METALLIZING;

DAMASCENE METALLIZATION; EMBEDDED DYNAMIC RANDOM ACCESS MEMORY; SELF ALIGNED CONTACTS;

VLSI CIRCUITS;

EID: 0033715433     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)