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Volumn 34, Issue 8, 1999, Pages 1084-1090

Precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIFFERENTIAL AMPLIFIERS; DYNAMIC RANDOM ACCESS STORAGE; INTEGRATED CIRCUIT TESTING; THRESHOLD VOLTAGE;

EID: 0033169550     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.777106     Document Type: Article
Times cited : (48)

References (6)
  • 2
    • 0029490113 scopus 로고
    • Well conception: A novel scaling limitation factor derived from DRAM retention time and its modeling
    • Dec.
    • T. Hamamoto, S. Sugiura, and S. Sawada, "Well conception: A novel scaling limitation factor derived from DRAM retention time and its modeling," in IEDM Dig. Tech. Papers, Dec. 1995, pp. 915-918.
    • (1995) IEDM Dig. Tech. Papers , pp. 915-918
    • Hamamoto, T.1    Sugiura, S.2    Sawada, S.3
  • 3
    • 0344507617 scopus 로고
    • Stabilization of voltage limiter circuit for high-density DRAM's using pole-zero compensation
    • Nov.
    • H. Tanaka, M. Aoki, J. Etoh, M. Horiguchi, K. Itoh, K. Kajigaya and T. Matsumoto, "Stabilization of voltage limiter circuit for high-density DRAM's using pole-zero compensation," IEICE Trans. Electron., vol. E75-C, no. 11, pp. 1333-1343, Nov. 1992.
    • (1992) IEICE Trans. Electron. , vol.E75-C , Issue.11 , pp. 1333-1343
    • Tanaka, H.1    Aoki, M.2    Etoh, J.3    Horiguchi, M.4    Itoh, K.5    Kajigaya, K.6    Matsumoto, T.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.