A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1697-1701

  Eto, Satoshi ^a,c   Matsumiya, Masato ^a,b,d   Takita, Masato ^a,e   Ishii, Yuki ^a,f   Nakamura, Toshikazu ^a,g   Kawabata, Kuninori ^a,h   Kano, Hideki ^a   Kitamoto, Ayako ^a   Ikeda, Toshimi ^a   Koga, Toru ^a   Higashiho, Mitsuhiro ^a   Serizawa, Yuji ^a   Itabashi, Kazuo ^a   Tsuboi, Osamu ^a   Yokoyama, Yuji ^a   Taguchi, Masao ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

^b IEEE

^c UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

^d NAGOYA INSTITUTE OF TECHNOLOGY   (Japan)

^e HOKKAIDO INSTITUTE OF TECHNOLOGY   (Japan)

^f TOKYO CITY UNIVERSITY   (Japan)

^g OSAKA UNIVERSITY   (Japan)

^h TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

1 Gb SDRAM; Clock recovery; Digital type DLL; Ground level precharge; Half V cc precharge; Low power operation; Low voltage operation; Nonboosted word line; Quantization error; Vernier type DLL

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL CIRCUITS; ERROR ANALYSIS;

DELAY LOCKED LOOPS (DLL); SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032204697     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726562     Document Type: Article

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