Self-aligned dual-gate single-electron transistors

Japanese Journal of Applied Physics

Volumn 47, Issue 4 PART 2, 2008, Pages 3118-3122

  Kang, Sangwoo ^a   Kim, Dae Hwan ^b   Park, Il Han ^a   Kim, Jin Ho ^a   Lee, Joung Eob ^a   Lee, Jong Duk ^a   Park, Byung Gook ^a  

^a Seoul National University   (South Korea)

^b Kookmin University   (South Korea)

Author keywords

CMOS compatibility; Coulomb oscillation; Dual gate; Room temperature operation; Self alignment; Side gate length dependency; Single electron transistor

Indexed keywords

ALIGNMENT; CAPACITANCE MEASUREMENT; ELECTRON TUNNELING; ELECTRONS; FABRICATION; GALERKIN METHODS; METAL RECOVERY; PARAMETER EXTRACTION; SEMICONDUCTING SILICON COMPOUNDS; STATIC RANDOM ACCESS STORAGE; TEMPERATURE MEASUREMENT; TRANSIENTS; TRANSISTORS; TUNNELING (EXCAVATION);

CMOS COMPATIBILITY; COULOMB OSCILLATION; DUAL-GATE; ROOM TEMPERATURE OPERATION; SELF-ALIGNMENT; SIDE GATE LENGTH DEPENDENCY; SINGLE-ELECTRON TRANSISTOR;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 54249162977     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.47.3118     Document Type: Article

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