Complementary symmetry nanowire logic circuits: Experimental demonstrations and in silico optimizations

ACS Nano

Volumn 2, Issue 9, 2008, Pages 1789-1798

  Sheriff, Bonnie A ^a   Wang, Dunwei ^a,c   Heath, James R ^a   Kurtin, Juanita N ^b  

^a California Institute of Technology   (United States)

^b INTEL CORPORATION   (United States)

^c BOSTON COLLEGE   (United States)

Author keywords

Circuit simulations; Complementary circuits; Field effect; Nanotechnology; Nanowire; Transistors

Indexed keywords

CIRCUIT SIMULATION; ELECTRIC WIRE; ENERGY EFFICIENCY; FIELD EFFECT TRANSISTORS; LOGIC GATES; MESFET DEVICES; NANOSTRUCTURED MATERIALS; NANOSTRUCTURES; NANOWIRES; NETWORKS (CIRCUITS); SIGNAL PROCESSING; SILICON; SWITCHING CIRCUITS; SWITCHING THEORY; TABLE LOOKUP; TRANSISTORS;

BOOLEAN LOGICS; COMPLEMENTARY; COMPLEMENTARY CIRCUITS; DEVICE FABRICATION PROCESSES; DEVICE FLUCTUATIONS; ENERGY-EFFICIENT; FET PROPERTIES; FIELD EFFECT; HIGH GAINS; IN SILICO; LARGE-SCALE; LOOK-UP TABLES; MODELING; NOISE MARGINS; OPTIMIZING; OUTPUT LOGICS; SIGNAL RESTORATIONS; SILICON NANOWIRES; SINGLE NANOWIRES; VOLTAGE LEVELS; VOLTAGE SIGNALS; XOR GATES;

LOGIC CIRCUITS;

NANOTUBE;

ARTICLE; CHEMISTRY; COMPUTER AIDED DESIGN; ELECTRONICS; EQUIPMENT; EQUIPMENT DESIGN; EVALUATION; INSTRUMENTATION; MICROELECTRODE; NANOTECHNOLOGY; SEMICONDUCTOR; SIGNAL PROCESSING;

COMPUTER-AIDED DESIGN; ELECTRONICS; EQUIPMENT DESIGN; EQUIPMENT FAILURE ANALYSIS; MICROELECTRODES; NANOTECHNOLOGY; NANOTUBES; SIGNAL PROCESSING, COMPUTER-ASSISTED; TRANSISTORS;

EID: 54249155551     PISSN: 19360851     EISSN: 1936086X     Source Type: Journal    
DOI: 10.1021/nn800025q     Document Type: Article

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