Scalability and parallel execution of warp processing: Dynamic hardware/software partitioning

International Journal of Parallel Programming

Volumn 36, Issue 5, 2008, Pages 478-492

  Lysecky, Roman ^a  

^a University of Arizona   (United States)

Author keywords

Dynamically adaptable systems; Embedded systems; Hardware software partitioning; Warp processing

Indexed keywords

ARM PROCESSORS; CUSTOM HARDWARES; DYNAMICALLY ADAPTABLE SYSTEMS; EMBEDDED PROCESSORS; HARDWARE/SOFTWARE PARTITIONING; LOW POWERS; NOVEL ARCHITECTURE; ON CHIPS; PARALLEL EXECUTIONS; PROCESSOR EXECUTION; SOFTWARE EXECUTION; WARP PROCESSING;

COMPUTER AIDED LOGIC DESIGN; COMPUTER SOFTWARE SELECTION AND EVALUATION; EMBEDDED SYSTEMS; ENERGY MANAGEMENT; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INDUSTRIAL RESEARCH; INTEGRATED CIRCUITS; SCALABILITY;

WEAVING;

EID: 52549086188     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10766-008-0079-0     Document Type: Article

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