Layout-design methodology of 0.246-μm2-embedded 6T-SRAM for 45-nm high-performance system LSIs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 28-29

  Morimoto, R ^a   Kimura, T ^b   Okayama, Y ^b   Hirai, T ^b   Maeda, H ^a   Oshima, K ^a   Watanabe, R ^b   Fukui, H ^b   Tsunoda, Y ^b   Togo, M ^b   Kanai, S ^a   Shino, S ^a   Hoshino, T ^c   Shimazaki, K ^c   Nakazawa, M ^a   Nakazawa, K ^a   Takasu, Y ^b   Yamasaki, H ^b   Inokuma, H ^b   Taniguchi, S ^b   Fujimaki, T ^b   Yamada, H ^b   Watanabe, S ^b   Muramatsu, S ^b   Iwasa, S ^b   Nagaoka, K ^a   Mimotogi, S ^b   Iwamoto, T ^b   Nii, H ^b   Sogo, Y ^a   Ohno, K ^a   Yoshida, K ^b   Sunouchi, K ^b   Ikeda, M ^b   Iwai, M ^b   Kitano, T ^b   Naruse, H ^b   Enomoto, Y ^a   Imai, K ^b   Yamada, S ^b   Saito, M ^a   Kuwata, T ^b   Matsuoka, F ^b   Nagashima, N ^a   more..

^a Semiconductor Business Group

^b TOSHIBA CORPORATION   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

High performance process platform; Layout design; SRAM

Indexed keywords

DESIGN METHODOLOGIES; VLSI TECHNOLOGIES;

EID: 47249114808     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339714     Document Type: Conference Paper

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