A scalable architecture for variable block size motion estimation on field-programmable gate arrays

Canadian Conference on Electrical and Computer Engineering

Volumn , Issue , 2008, Pages 1303-1308

  Moorthy, Theepan ^a   Ye, Andy ^a  

^a RYERSON UNIVERSITY   (Canada)

Author keywords

Field programmable gate arrays; H.264 AVC; Variable block size motion estimation

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; APPLICATIONS; ARCHITECTURE; COMPUTER SYSTEMS; DIGITAL TELEVISION; ELECTRONICS INDUSTRY; ENCODING (SYMBOLS); ESTIMATION; INTEGRATED CIRCUITS; LAWS AND LEGISLATION; LOGIC GATES; MOTION ESTIMATION; MOTION PICTURE EXPERTS GROUP STANDARDS; STANDARDS; TECHNOLOGY; TELEVISION BROADCASTING; VECTOR QUANTIZATION;

COMPUTING UNITS; DESIGN RE-USE; DEVICE UTILIZATION; DIGITAL SYSTEMS; ELECTRICAL AND COMPUTER ENGINEERING; FIELD-PROGRAMMABLE GATE ARRAYS; H.264/AVC; HIGH RESOLUTIONS; LOW COSTS; LOW RESOLUTION; MEMORY BANDWIDTHS; PERFORMANCE GAP; SCALABLE ARCHITECTURES; VARIABLE BLOCK SIZE MOTION ESTIMATION; VIDEO ENCODING SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 51849097416     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCECE.2008.4564750     Document Type: Conference Paper

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